ICS85304AG-01LFT IDT, Integrated Device Technology Inc, ICS85304AG-01LFT Datasheet - Page 3

• Manufacturer Part Number: ICS85304AG-01LFT
• Description: IC FANOUT BUFFER 1-5 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS85304AG-01LFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 650MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85304AG-01LFT

Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLKx/nCLKx inputs as described in Table 3B.
Figure 1.
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
nCLK[0:1]
CLK[0:1]
CLK_EN
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
nQ[0:4]
Biased; NOTE 1
Biased; NOTE 1
Q[0:4]
CLK0 or CLK1
CLK_EN
0
1
0
1
CLK_EN
0
0
1
1
Inputs
Timing Diagram
nCLK0 or nCLK1
Biased; NOTE 1
Biased; NOTE 1
Disabled
1
0
0
1
CLK_SEL
Inputs
0
1
0
1
Q[0:4]
HIGH
HIGH
HIGH
LOW
LOW
LOW
Outputs
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
3
nQ[0:4]
HIGH
HIGH
HIGH
LOW
LOW
LOW
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Differential to Differential
Differential to Differential
Enabled
Input to Output Mode
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Q0:Q4
ICS85304AG-01 REV. E JULY 8, 2008
Outputs
Disabled; HIGH
Disabled; HIGH
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
nQ0:nQ4
Enabled
Enabled
Inverting
Inverting
Polarity