ICS85304AG-01LF IDT, Integrated Device Technology Inc, ICS85304AG-01LF Datasheet

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ICS85304AG-01LF

Manufacturer Part Number
ICS85304AG-01LF
Description
IC FANOUT BUFFER 1-5 20-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet

Specifications of ICS85304AG-01LF

Number Of Circuits
1
Ratio - Input:output
2:5
Differential - Input:output
Yes/Yes
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVPECL
Frequency - Max
650MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
650MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
85304AG-01LF
LOW SKEW, 1-TO-5, Differential-TO-
3.3V LVPECL FANOUT BUFFER
General Description
CLKx, nCLKx pairs can accept most standard differential input
levels. The clock enable is internally synchronized to eliminate
runt clock pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS85304-01 ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
CLK_SEL
HiPerClockS™
CLK_EN
ICS
nCLK0
nCLK1
CLK0
CLK1
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
The ICS85304-01 is a low skew, high performance
1-to-5 Differential-to-3.3V LVPECL fanout buffer and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The
ICS85304-01 has two selectable clock inputs. The
0
1
0
1
D
LE
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
Features
Five 3.3V differential LVPECL output pairs
Selectable differential CLKx/nCLKx input pairs
CLKx/nCLKx input pairs can accept the following differential
levels: LVDS, LVPECL, LVHSTL, SSTL and HCSL levels
Maximum output frequency: 650MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLKx inputs
Output skew: 35ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 2.1ns (maximum)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
6.5mm x 4.4mm x 0.925mm
Pin Assignment
nQ4
nQ0
nQ1
nQ2
nQ3
20-Lead TSSOP
Q0
Q2
Q3
Q4
Q1
package body
ICS85304-01
G Package
Top View
1
2
3
4
5
6
7
8
9
10
ICS85304AG-01 REV. E JULY 8, 2008
20
19
18
17
16
15
14
13
12
11
V
V
nCLK1
CLK1
nCLK0
CLK_SEL
CLK_EN
V
V
CC
CC
EE
CC
ICS85304-01

Related parts for ICS85304AG-01LF

ICS85304AG-01LF Summary of contents

Page 1

... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment nQ0 nQ1 Q0 nQ0 nQ2 Q1 nQ3 nQ1 nQ4 Q2 nQ2 Q3 nQ3 6.5mm x 4.4mm x 0.925mm Q4 nQ4 1 ICS85304- CLK_EN nCLK1 CLK1 nCLK0 CLK_SEL ICS85304-01 20-Lead TSSOP package body G Package Top View ICS85304AG-01 REV. E JULY 8, 2008 ...

Page 2

... Inverting differential clock input. Synchronizing clock enable. When HIGH, clock outputs follow clock input. Pullup When LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH. LVTTL/LVCMOS interface levels. Test Conditions 2 Minimum Typical Maximum ICS85304AG-01 REV. E JULY 8, 2008 Units pF Ω k Ω k ...

Page 3

... Q0:Q4 nQ0:nQ4 Disabled; LOW Disabled; HIGH Disabled; LOW Disabled; HIGH Enabled Enabled Enabled Enabled Enabled Input to Output Mode Differential to Differential Non-Inverting Differential to Differential Non-Inverting Single-Ended to Differential Non-Inverting Single-Ended to Differential Non-Inverting Single-Ended to Differential Single-Ended to Differential ICS85304AG-01 REV. E JULY 8, 2008 Polarity Inverting Inverting ...

Page 4

... Test Conditions Minimum 3.135 = 3.3V ± 5%, V =0V -40°C to 85° Test Conditions Minimum 3.465V 3.465V 3.465V -150 3.465V Typical Maximum 3.3 3.465 55 Typical Maximum 2 3.765 -0.3 0.8 5 150 -5 ICS85304AG-01 REV. E JULY 8, 2008 Units V mA Units V V µA µA µA µA ...

Page 5

... -40°C to 85°C A Minimum Typical Maximum V – 1 – 2 0.6 0.85 Minimum Typical Maximum 1.0 300 48 50 ICS85304AG-01 REV. E JULY 8, 2008 Units 5 µA 150 µA µA µA 1.3 V – 0. Units – 1.0 µA – 1.7 µA V Units 650 MHz 2 150 ps 700 ...

Page 6

... IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER V CC SCOPE Qx nCLK0, nCLK1 CLK0, CLK1 nQx V EE Differential Input Level Par t 1 nQx Qx Par t 2 nQy Qy Part-to-Part Skew nQ[0:4] Q[0:4] Output Duty Cycle/Pulse Width/Period Cross Points PP tsk(pp PERIOD t PW odc = x 100% t PERIOD ICS85304AG-01 REV. E JULY 8, 2008 CMR ...

Page 7

... For example, if the input clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and CC R2/R1 = 0.609. IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER 80 20 Single Ended Clock Input Figure 1. Single-Ended Signal Driving Differential Input CLKx V_REF nCLKx C1 0. ICS85304AG-01 REV. E JULY 8, 2008 ...

Page 8

... R2 50 Driven by a 3.3V LVPECL Driver 100 LVDS Driven by a 3.3V LVDS Driver 2. 120 120 SSTL R1 R2 120 120 Driven by a 2.5V SSTL Driver ICS85304AG-01 REV. E JULY 8, 2008 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver 3.3V CLK nCLK HiPerClockS ...

Page 9

... Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FIN RTT Figure 3B. 3.3V LVPECL Output Termination 9 3.3V 125 125 FOUT ICS85304AG-01 REV. E JULY 8, 2008 FIN ...

Page 10

... 3.465V * 55mA = 190.57mW EE_MAX * Pd_total + for 20 Lead TSSOP, Forced Convection θ by Velocity JA 0 114.5°C/W 73.2°C/W 10 must be used. Assuming no air flow JA 200 500 98.0°C/W 88.0°C/W 66.6°C/W 63.5°C/W ICS85304AG-01 REV. E JULY 8, 2008 ...

Page 11

... Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER V OUT – 1.0V CC_MAX = V – 1.7V CC_MAX ] * (V – [(2V – (V CC_MAX OH_MAX – [(2V – (V CC_MAX OL_MAX CC_MAX L 11 – V ))/ – V CC_MAX OH_MAX CC_MAX L – V ))/ – V OL_MAX CC_MAX L ICS85304AG-01 REV. E JULY 8, 2008 ) = OH_MAX ) = OL_MAX ...

Page 12

... All Dimensions in Millimeters Symbol Minimum 0.05 A2 0.80 b 0.19 c 0. 0.45 α 0° aaa Reference Document: JEDEC Publication 95, MO-153 12 500 88.0°C/W 63.5°C/W Maximum 20 1.20 0.15 1.05 0.30 0.20 6.60 6.40 Basic 4.50 0.65 Basic 0.75 8° 0.10 ICS85304AG-01 REV. E JULY 8, 2008 ...

Page 13

... Shipping Packaging 20 Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP 13 Temperature Tube 0°C to 70°C 2500 Tape & Reel 0°C to 70°C Tube 0°C to 70°C 2500 Tape & Reel 0°C to 70°C ICS85304AG-01 REV. E JULY 8, 2008 ...

Page 14

... CC - 2.0µA; 1.6µA max 1.7µA max typ max. CYCLE CYCLE , and V rows CMR values changed from V - 0.85V max -1.3V ± 0.135V to EE ICS85304AG-01 REV. E JULY 8, 2008 Date 5/14/01 5/22/01 8/21/01 10/17/01 11/2/01 12/28/01 5/30/02 8/26/02 6/17/04 6/20/08 7/8/08 ...

Page 15

ICS85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and ...

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