AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 55

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Reg.
Addr.
(Hex) Bit(s) Name
49
(4B)
(4D)
(4F)
(51)
(53)
(55)
(57)
49
(4B)
(4D)
(4F)
(51)
(53)
(55)
(57)
49
(4B)
(4D)
(4F)
(51)
(53)
(55)
(57)
58
58
58
58
58
58
58
59
5A
5A
END
<5>
<6>
<7>
<0>
<1>
<2>
<3>
<4>
<6:5> FUNCTION Pin
<7>
<7:0>
<0>
<7:1>
Force
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
Nosync
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
Bypass Divider
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
SYNC Detect Enable 1 = Enable SYNC Detect (Default = 0b)
SYNC Select
Soft SYNC
Dist Ref Power-
Down
SYNC Power-Down 1 = Power-Down the SYNC (Default = 0b)
Select
Update Registers
Description
Forces Individual Outputs to the State Specified in Start (Above)
This Function Requires That Nosync (Below) Also Be Set (Default = 0b)
Ignore Chip-Level Sync Signal (Default = 0b)
Bypass and Power-Down Divider Logic; Route Clock Directly to Output (Default = 0b)
1 = Raise Flag if Slow Clocks Are Out-of-Sync by 0.5 to 1 High Speed Clock Cycles
0 (Default) = Raise Flag if Slow Clocks Are Out-of-Sync by 1 to 1.5 High Speed Clock Cycles
Soft SYNC bit works the same as the FUNCTION pin when in SYNCB mode, except that this bit’s polarity is
reversed. That is, a high level forces selected outputs into a known state, and a high > low transition
triggers a sync (default = 0b).
1 = Power-Down the References for the Distribution Section (Default = 0b)
<6>
0
0
1
1
Not Used
Not Used
A 1 written to this bit updates all registers and transfers all serial control port register buffer contents to
the control registers on the next rising SCLK edge. This is a self-clearing bit; a 0 does not have to be
written to clear it.
Not Used
Rev. A | Page 55 of 60
<5>
0
1
0
1
Function
RESETB (Default)
SYNCB
Test Only; Do Not Use
PDB
AD9510