AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 34

IC CLOCK DIST 8OUT PLL 64LFCSP

AD9510BCPZ

Manufacturer Part Number
AD9510BCPZ
Description
IC CLOCK DIST 8OUT PLL 64LFCSP
Manufacturer
Analog Devices Inc
Type
Fanout Buffer (Distribution), Divider, PLLr
Datasheet

Specifications of AD9510BCPZ

Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
Yes/Yes
Input
Clock
Output
CMOS, LVDS, LVPECL
Frequency - Max
1.2GHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.2GHz
Clock Ic Type
Clock Distribution
Ic Interface Type
Serial
Frequency
1.2GHz
No. Of Outputs
8
No. Of Multipliers / Dividers
8
Supply Voltage Range
3.135V To 3.465V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
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Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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Quantity:
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AD9510
Setting the Divide Ratio
The divide ratio is determined by the values written via the SCP
to the registers that control each individual output, OUT0 to
OUT7. These are the even numbered registers beginning at 48h
and going through 56h. Each of these registers is divided into
bits that control the number of clock cycles that the divider
output stays high (high_cycles <3:0>) and the number of clock
cycles that the divider output stays low (low_cycles <7:4>). Each
value is 4 bits and has the range of 0 to 15.
The divide ratio is set by
Example 1:
Set the Divide Ratio = 2
Table 17. Duty Cycle and Divide Ratio
Divide Ratio
2
3
3
4
4
4
5
5
5
5
6
6
6
6
6
7
7
7
7
high_cycles = 0
low_cycles = 0
Divide Ratio = (0 + 1) + (0 + 1) = 2
Divide Ratio = (high_cycles + 1) + (low_cycles + 1)
Duty Cycle (%)
50
67
33
50
75
25
60
40
80
20
50
67
33
83
17
57
43
71
29
LO <7:4>
0
0
1
1
0
2
1
2
0
3
2
1
3
0
4
2
3
1
4
48h to 56h
HI<3:0>
0
1
0
1
2
0
2
1
3
0
2
3
1
4
0
3
2
4
1
Rev. A | Page 34 of 60
Example 2:
Set Divide Ratio = 8
Note that a Divide Ratio of 8 may also be obtained by setting:
Although the second set of settings produces the same divide
ratio, the resulting duty cycle is not the same.
Setting the Duty Cycle
The duty cycle and the divide ratio are related. Different
divide ratios have different duty cycle options. For example, if
Divide Ratio = 2, the only duty cycle possible is 50%. If the
Divide Ratio = 4, the duty cycle may be 25%, 50%, or 75%.
The duty cycle is set by
Duty Cycle = (high_cycles + 1)/((high_cycles + 1) + (low_cycles + 1))
See Table 17 for the values for the available duty cycles for each
divide ratio.
Divide Ratio
7
7
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
10
10
high_cycles = 3
low_cycles = 3
Divide Ratio = (3 + 1) + (3 + 1) = 8
high_cycles = 2
low_cycles = 4
Divide Ratio = (2 + 1) + (4 + 1) = 8
Duty Cycle (%)
86
14
50
63
38
75
25
88
13
56
44
67
33
78
22
89
11
50
60
LO <7:4>
0
5
3
2
4
1
5
0
6
3
4
2
5
1
6
0
7
4
3
48h to 56h
HI<3:0>
5
0
3
4
2
5
1
6
0
4
3
5
2
6
1
7
0
4
5

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