AD9510BCPZ Analog Devices Inc, AD9510BCPZ Datasheet - Page 49

• Manufacturer Part Number: AD9510BCPZ
• Description: IC CLOCK DIST 8OUT PLL 64LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9510BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 8
• No. Of Multipliers / Dividers: 8
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9510-VCO/PCBZ - BOARD EVALUATION FOR AD9510AD9510/PCBZ - BOARD EVALUATION FOR AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Reg.
Addr.
(Hex) Bit(s) Name
00
00
00
00
00
01
02
03
04
04
05
05
06
07
07
07
07
07
08
REGISTER MAP DESCRIPTION
Table 24 lists the AD9510 control registers by hexadecimal address. A specific bit or range of bits within a register is indicated by angle
brackets. For example, <3> refers to Bit 3, while <5:2> refers to the range of bits from Bit 5 through Bit 2. Table 24 describes the
functionality of the control registers on a bit-by-bit basis. For a more concise (but less descriptive) table, see Table 23.
Table 24. AD9510 Register Descriptions
<3:0>
<4>
<5>
<6>
<7>
<7:0>
<7:0>
<7:0>
<5:0> A Counter
<7:6>
<4:0> B Counter MSBs
<7:5>
<7:0> B Counter LSBs
<1:0>
<2>
<4:3>
<6:5> LOR Initial Lock
<7>
<1:0> Charge Pump
Serial Control Port
Configuration
Long Instruction
Soft Reset
LSB First
SDO Inactive
(Bidirectional
Mode)
Not Used
PLL Settings
LOR Enable
Detect Delay
Mode
Description
Any changes to this register takes effect immediately. Register 5Ah<0> Update Registers does not
have to be written.
Not Used.
When this bit is set (1), the instruction phase is 16 bits. When clear (0), the instruction phase is 8 bits.
The default, and only, mode for this part is long instruction (Default = 1b).
When this bit is set (1), the chip executes a soft reset, restoring default values to the internal registers,
except for this register, 00h. This bit is not self-clearing. A clear (0) has to be written to it in order
to clear it.
When this bit is set (1), the input and output data is oriented as LSB first. Additionally, register addressing
increments. If this bit is clear (0), data is oriented as MSB first and register addressing decrements.
(Default = 0b, MSB first.)
When set (1), the SDO pin is tri-state and all read data goes to the SDIO pin. When clear (0), the SDO is
active (unidirectional mode). (Default = 0b.)
Not Used
Not Used
Not Used
6-Bit A Counter <5:0>
Not Used
13-Bit B Counter (MSB) <12:8>
Not Used
13-Bit B Counter (LSB) <7:0>
Not Used
1 = Enables the Loss-of-Reference (LOR) Function; (Default = 0b)
Not Used
LOR Initial Lock Detect Delay. Once a lock detect is indicated, this is the number of phase frequency
detector (PFD) cycles that occur prior to turning on the LOR monitor.
<6>
0
0
1
1
Not Used
<1>
0
0
1
1
Rev. A | Page 49 of 60
<5>
0
1
0
1
<0>
0
1
0
1
LOR Initial Lock Detect Delay
3 PFD Cycles (Default)
6 PFD Cycles
12 PFD Cycles
24 PFD Cycles
Charge Pump Mode
Tri-Stated (Default)
Pump-Up
Pump-Down
Normal Operation
AD9510