ICS83023AMILF IDT, Integrated Device Technology Inc, ICS83023AMILF Datasheet

XLATOR/BUFFER DUAL 1:1 8-SOIC

ICS83023AMILF

Manufacturer Part Number
ICS83023AMILF
Description
XLATOR/BUFFER DUAL 1:1 8-SOIC
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Translatorr
Datasheet

Specifications of ICS83023AMILF

Number Of Circuits
2
Ratio - Input:output
1:1
Differential - Input:output
Yes/No
Input
HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVCMOS, LVTTL
Frequency - Max
350MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC
Frequency-max
350MHz
Number Of Outputs
2
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Propagation Delay Time
2.4ns
Operating Supply Voltage (min)
3V
Mounting
Surface Mount
Pin Count
8
Operating Supply Voltage (typ)
3.3V
Package Type
SOIC N
Duty Cycle
57%
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1102
800-1102-5
800-1102
83023AMILF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS83023AMILF
Manufacturer:
IDT
Quantity:
2 000
Part Number:
ICS83023AMILFT
Manufacturer:
IDT
Quantity:
20 000
G
The ICS83023I is a dual, 1-to-1 Differential-to-LVCMOS
most differential signal types (LVDS, LVHSTL, LVPECL, SSTL,
and HCSL) and translate into two single-ended LVCMOS
outputs. The small 8-lead SOIC footprint makes this device
ideal for use in applications with limited board space.
B
83023AMI
Translator/Fanout Buffer. The differential inputs can accept
LOCK
ENERAL
nCLK0
nCLK1
CLK0
CLK1
D
IAGRAM
D
ESCRIPTION
Q0
Q1
www.idt.com
D
IFFERENTIAL
1
Features
P
Two LVCMOS / LVTTL outputs
Two differential CLKx, nCLKx input pairs
CLK, nCLK pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 350MHz (typical)
Output skew: 60ps (maximum)
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.14ps (typical)
Small 8 lead SOIC package saves board space
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
IN
A
3.8mm x 4.8mm x 1.47mm package body
SSIGNMENT
-
TO
-LVCMOS T
nCLK0
nCLK1
CLK0
CLK1
ICS83023I
8-Lead SOIC
M Package
Top View
1
2
3
4
8
7
6
5
RANSLATOR
V
Q0
Q1
GND
DD
ICS83023I
D
UAL
REV. B JULY 29, 2010
/B
, 1-
UFFER
TO
-1

Related parts for ICS83023AMILF

ICS83023AMILF Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS83023I is a dual, 1-to-1 Differential-to-LVCMOS Translator/Fanout Buffer. The differential inputs can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate into two single-ended LVCMOS outputs. The small 8-lead SOIC footprint ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, JA Storage Temperature, T -65°C to 150°C STG T 3A ABLE ...

Page 4

3.3V±0.3V, T ABLE HARACTERISTICS ...

Page 5

The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often ...

Page 6

P ARAMETER 1.65V ± 0.15V V DD LVCMOS GND -1.65V ± 0.15V 3. UTPUT OAD EST IRCUIT tsk( UTPUT KEW nCLK0, nCLK1 CLK0, CLK1 V ...

Page 7

IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...

Page 8

IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V meet the V and V input requirements. Figures CMR show interface examples for ...

Page 9

ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second ...

Page 10

ACKAGE UTLINE UFFIX FOR EAD T ABLE Reference Document: JEDEC Publication 95, MS-012 83023AMI D - IFFERENTIAL TO SOIC ACKAGE IMENSIONS ...

Page 11

ABLE RDERING NFORMATION ...

Page 12

...

Page 13

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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