W40S11-02H Cypress Semiconductor Corp, W40S11-02H Datasheet - Page 6

• Manufacturer Part Number: W40S11-02H
• Description: IC CLK BUFF 10OUT SDRAM 28SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Bufferr

Specifications of W40S11-02H

• Output: CMOS
• Frequency - Max: 133MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Input: -
• Other names: 428-1401

Signaling Requirements
As shown in Figure 2, valid data bits are defined as stable logic
0 or 1 condition on the data line during a clock HIGH (logic 1)
pulse. A transitioning data line during a clock HIGH pulse may
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write sequence is initiated by a “start bit” as shown in Figure
3. A “stop bit” signifies that a transmission has ended.
As stated previously, the W40S11-02 sends an “acknowledge”
pulse after receiving eight data bits in each byte as shown in
Figure 4.
S C L O C K
S D A T A
S C L O C K
SDATA
Start
Bit
Figure 3. Serial Data Bus Start and Stop Bit
Figure 2. Serial Data Bus Valid Data Bit
Valid
Data
Bit
of Data Allowed
Change
6
Sending Data to the W40S11-02
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the receipt of each data bit (registers are not double buff-
ered). Partial transmission is allowed meaning that a transmis-
sion can be truncated as soon as the desired data bits are
transmitted (remaining registers will be unmodified). Transmis-
sion is truncated with either a stop bit or new start bit (restart
condition).
Stop
Bit
W40S11-02