W40S11-23G Cypress Semiconductor Corp, W40S11-23G Datasheet
W40S11-23G
Manufacturer Part Number
W40S11-23G
Description
Manufacturer
Cypress Semiconductor Corp
Specifications of W40S11-23G
Number Of Outputs
13
Operating Supply Voltage (max)
3.47V
Operating Temp Range
0C to 70C
Operating Supply Voltage (min)
3.14V
Mounting
Surface Mount
Pin Count
28
Operating Supply Voltage (typ)
3.3V
Package Type
SOIC
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W40S11-23G
Manufacturer:
ICWORKS
Quantity:
20 000
1W40S11-23
Features
Overview
The Cypress W40S11-23 is a low-voltage, thirteen-output
clock buffer. Output buffer impedance is approximately 15 ,
which is ideal for driving SDRAM DIMMs.
Cypress Semiconductor Corporation
• Thirteen skew-controlled CMOS clock outputs
• Supports three SDRAM DIMMs
• Ideal for high-performance systems designed around
• SMBus serial configuration interface
• Clock Skew between any two outputs is less than 250 ps
• 1- to 5-ns propagation delay
• DC to 133-MHz operation
• Single 3.3V supply voltage
• Low power CMOS design packaged in a 28-pin, 300-mil
Block Diagram
(SDRAM0:12)
Intel’s latest chip set
SOIC (Small Outline Integrated Circuit), 28-pin, 173-mil
(Thin Shrink Small Outline Package), and 28-pin,
209-mil SSOP (Small Shrink Outline Package)
SCLOCK
BUF_IN
SDATA
Serial Port
Device Control
•
3901 North First Street
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
Key Specifications
Supply Voltages:........................................... V
Operating Temperature:.................................... 0°C to +70°C
Input Threshold: .................................................. 1.5V typical
Maximum Input Voltage: .......................................V
Input Frequency:............................................... 0 to 133 MHz
BUF_IN to SDRAM0:12 Propagation Delay: ......1.0 to 5.0 ns
Output Edge Rate:..............................................
Output Clock Skew: .................................................. ±250 ps
Output Duty Cycle: .................................. 45/55% worst case
Output Impedance:...............................................15 typical
Output Type: ................................................ CMOS rail-to-rail
Pin Configuration
Note:
1.
•
SDRAM12
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDATA
BUF_IN
Internal pull-up resistor of 250K on SDATA and SCLOCK inputs
(not CMOS level).
San Jose
GND
GND
VDD
VDD
VDD
[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Clock Buffer/Driver
•
CA 95134
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
W40S11-23
•
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
SDRAM8
GND
VDD
SDRAM7
SDRAM6
GND
GND
SCLOCK
DD
408-943-2600
April 6, 2001
= 3.3V±5%
DD
>1.5 V/ns
[1]
+ 0.5V
[+] Feedback
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