SI5013-BM Silicon Laboratories Inc, SI5013-BM Datasheet - Page 15

• Manufacturer Part Number: SI5013-BM
• Description: IC CLOCK/DATA RECOVERY 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SI5013-BM

• Input: Differential
• Output: CML
• Frequency - Max: 675MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 675MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1122

a simple circuit that may be used to set a fixed level of
LOS signal hysteresis for the Si5013 CDR. The value of
R1 may be chosen to provide a range of hysteresis from
3 to 8 dB where a nominal value of 800 Ω adjusts the
hysteresis level to approximately 6 dB. Use a value of
500 Ω or 1000 Ω for R1 to provide 3 dB or 8 dB of
hysteresis, respectively.
Hysteresis is defined as the ratio of the LOS deassert
level (LOSD) and the LOS assert level (LOSA). The
hysteresis in decibels is calculated as 20log(LOSD/
LOSA).
Bit Error Rate (BER) Detection
The Si5013 uses a proprietary Silicon Laboratories®
algorithm to generate a bit error rate (BER) alarm on the
BER_ALM pin if the observed BER is greater than a
user programmable threshold. Bit error detection relies
on the input data edge timing; edges occurring outside
of the expected event window are counted as bit errors.
The BER threshold is programmed by applying a
voltage to the BER_LVL pin between 500 mV and
2.25 V corresponding to a BER of approximately 10
and 10
BER_LVL maps to the BER as follows: log10(BER) =
(4 x BER_LVL) –13. (BER_LVL is in volts; BER is in bits
per second.)
Data Slicing Level
The Si5013 provides the ability to externally adjust the
slicing level for applications that require bit error rate
(BER) optimization. Adjustments in slicing level of
±15 mV (relative to the internally set input common
mode voltage) are supported. The slicing level is set by
applying a voltage between 0.75 and 2.25 V to the
SLICE_LVL input. The voltage present on SLICE_LVL
maps to the slicing level as follows:
where V
voltage applied to the SLICE_LVL pin.
When SLICE_LVL is driven below 500 mV, the slicing
level adjustment is disabled, and the slicing level is set
to the cross-point of the differential input signal.
PLL Performance
The PLL implementation used in the Si5013 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 3, September 2000 and ITU-T G.958.
Jitter Tolerance
The Si5013’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 8. This mask
SLICE
–6
, respectively. The voltage present on
V
is the slicing level, and V
SLICE
=
(
------------------------------------------------------ -
V
SLICE_LVL
50
–
1.5 V
SLICE_LVL
)
is the
–10
Rev. 1.3
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Note: There are no entries in the mask table for the data rate
Jitter Transfer
The
specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency.
These measurements are made with an input test signal
that is degraded with sinusoidal jitter whose magnitude
is defined by the mask in Figure 9.
Jitter (UI
Sinusoidal
Transfer
Input
Figure 8. Jitter Tolerance Specification
Jitter
Figure 9. Jitter Transfer Specification
corresponding to OC-24 as that rate is not specified by
either GR-253 or G.958.
Si5013
0.1 dB
SONET
Data Rate
OC-12
OC-3
0.15
1.5
PP
15
)
exceeds
f0
10
10
F0
(Hz)
Acceptable
Range
SONET
Data Rate
OC-12
OC-3
f1
30
30
F1
(Hz)
Frequency
all
Frequency
f2
F2
(kHz)
300
300
relevant
Fc
130
500
Slope = 20 dB/Decade
Fc
(kHz)
f3
F3
(kHz)
25
6.5
20 dB/Decade
Si5013
ft
Slope
Bellcore/ITU
Ft
(kHz)
250
65
15