SI5013-D-GM Silicon Laboratories Inc, SI5013-D-GM Datasheet
SI5013-D-GM
Specifications of SI5013-D-GM
Related parts for SI5013-D-GM
SI5013-D-GM Summary of contents
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... PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5013 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (– °C). ...
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... Si5013 2 Rev. 1.6 ...
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... Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.15. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.16. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.17. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.18. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.19. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. Pin Descriptions: Si5013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Rev. 1.6 ...
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... Si5013 1. Detailed Block Diagram LOS BER_LVL Signal LOS_LVL Detect DIN+ Limiting Phase Amp Detector DIN– Slicing SLICE_LVL Control REFCLK± (optional) Bias REXT Generation 4 LTR BER_ALM RATESEL BER Monitor A/D DSP VCO n Lock Detection Calibration Rev. 1.6 DSQLCH DOUT+ Retime DOUT– ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5013 specifications are guaranteed when using the recommended application circuit (including component tolerance) of "3. Typical Application Schematic" on page 11. ...
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... Si5013 DOUT, CLKOUT Figure 3. DOUT and CLKOUT Rise/Fall Times RESET/Cal LOL DATAIN LOL DATAIN LOS Figure 4. PLL Acquisition Time t LOS Figure 5. LOS Response Rev. 1.6 80% 20% LOS Threshold Level ...
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... Load V OD Line-to-Line 100 Ω Load V OCM Line-to-Line R Single-ended OUT Rev. 1.6 Si5013 Min Typ Max Unit — 180 190 mA — 190 197 — 594 657 mW — 627 682 1.30 1.50 1.62 V 1.90 2.10 2. — 500 mV 10 — 1000 ...
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... Si5013 Table 3. AC Characteristics (Clock and Data 3.3 V ±5 – ° Parameter Symbol Output Clock Rate Output Rise Time—OC-12 Output Fall Time—OC-12 Output Clock Duty Cycle— OC-12/3 Clock to Data Delay t OC-12 OC-3 Clock to Data Delay t OC-12 OC-3 Input Return Loss ...
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... After falling edge of AQ PWRDN/CAL From the return of valid data T After falling edge of AQ PWRDN/CAL From the return of valid data See "4.4. Operation Without an External Ref- erence" on page 12. C TOL Rev. 1.6 Si5013 Min Typ Max Unit 60 — — — — — ...
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... Si5013 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... Loss-of-Signal Level Set Bit Error Rate BER Alarm LVTTL Loss-of-Signal Indicator Loss-of-Lock Indicator Si5013 100 VDD 10 kΩ (1%) Data Slice Level Set Level Set Rev. 1.6 Si5013 Indicator DOUT+ Recovered Data DOUT– CLKOUT+ Recovered Clock CLKOUT– 0.1 μF 11 ...
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... PLL the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the Si5013 uses the reference clock to center the VCO output frequency so that clock and data is recovered from the input data stream. The device self configures for operation with one of three reference clock frequencies ...
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... This produces a stable output clock as long as supply and temperature are constant. 4.8. Loss-of-Signal (LOS) The Si5013 indicates a loss-of-signal condition on the LOS output pin when the input peak-to-peak signal level on DIN falls below an externally controlled threshold. The LOS threshold range is specified in Table 3 on page 8 and is set by applying a voltage on the LOS_LVL pin ...
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... SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. 4.11.1. Jitter Tolerance The Si5013’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 8. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device ...
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... Device Grounding 20 dB/Decade Slope The Si5013 uses the GND pad on the bottom of the 28- pin micro leaded package (QFN) for device ground. This pad should be connected directly to the analog supply ground. See Figure 15 on page 19 and Figure 16 on page 23 for the ground (GND) pad location ...
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... Figure 11. Input Termination for DIN (ac coupled) 16 Si5013 2.5 V (±5%) 2.5 kΩ Ω RFCLK+ 100 Ω 10 kΩ 2.5 kΩ Ω RFCLK– 10 kΩ GND Si5013 2.5 V (±5 Ω DIN+ 50 Ω 5 kΩ 50 Ω 7.5 kΩ Ω DIN– GND Rev. 1.6 ...
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... Figure 13. Single-Ended Input Termination for DIN (ac coupled) Si5013 2.5 V (±5%) 2.5 kΩ RFCLK + 10 kΩ 2.5 kΩ RFCLK – 10 kΩ GND 2.5 V Si5013 (±5%) DIN+ 50 Ω 5 kΩ Ω 50 Ω 7.5 kΩ DIN– GND Rev. 1.6 Si5013 17 ...
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... Si5013 4.19. Differential Output Circuitry The Si5013 utilizes a current-mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 on page 7 ...
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... DOUT– TDI LOL Figure 15. Si5013 Pin Configuration Table 8. Si5013 Pin Descriptions I/O Signal Level I LVTTL Data Rate Select. This pin configures the onboard PLL for clock and data recovery at one of two user selectable data rates. See Table 7 for configuration settings. ...
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... Si5013 Table 8. Si5013 Pin Descriptions (Continued) Pin # Pin Name 5 REFCLK+ 6 REFCLK– 7 LOL 8 LTR 9 LOS 10 DSQLCH 11,14,18,21, VDD 25 12 DIN+ 13 DIN– 15 GND 20 I/O Signal Level I See Table 2 Differential Reference Clock (Optional). When present, the reference clock sets the center operating frequency of the DSPLL for clock and data recovery. Tie REFCLK+ to VDD and REFCLK– ...
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... Table 8. Si5013 Pin Descriptions (Continued) Pin # Pin Name 16 DOUT– 17 DOUT+ 19 RESET/CAL 20 REXT 22 CLKOUT– 23 CLKOUT+ 24 CLKDSBL 26 BER_LVL 27 BER_ALM 28 NC GND Pad, 2 GND I/O Signal Level O CML Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. ...
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... Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 3. These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Part Number Si5013 22 Voltage Pb-Free 3.3 Yes Die Revision— ...
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... Package Outline Figure 16 illustrates the package details for the Si5013. Table 9 lists the values for the dimensions shown in the illustration. For a pad layout recommendation please contact Silicon Laboratories. Figure 16. 28-Lead Quad Flat No-Lead (QFN) Controlling Dimension: mm Symbol θ aaa bbb ccc ...
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... Si5013 OCUMENT HANGE IST Revision 0.2 to Revision 1.0 Added Figure 4, “PLL Acquisition Time,” on page 6. Table 2 on page 7 Updated values: Supply Current Updated values: Power Dissipation Updated values: Common Mode Input Voltage (REFCLK) Updated values: Output Common Mode Voltage Table 3 on page 8 ...
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... Added note describing valid signal. Revised Figure 6, “LOS_LVL Mapping,” on page 13. Updated "4.10. Data Slicing Level" on page 14. Added Figure 8 on page 14. Revised text. Revision 1.5 to Revision 1.6 Added "7. Top Mark" on page 22. Updated "8. Package Outline" on page 23. Rev. 1.6 Si5013 25 ...
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... Si5013 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 7801 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...