SI5013-BM Silicon Laboratories Inc, SI5013-BM Datasheet
SI5013-BM
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SI5013-BM Summary of contents
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... PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5013 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (– °C). ...
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... Si5013 2 Rev. 1.3 ...
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... Bit Error Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Pin Descriptions: Si5013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Rev. 1.3 Si5013 Page 3 ...
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... Si5013 Detailed Block Diagram LOS BER_LVL Signal LOS_LVL Detect DIN+ Limiting Amp Detector DIN– Slicing SLICE_LVL Control REFCLK± (optional) Bias REXT Generation 4 LTR BER_ALM BER Monitor Phase A/D DSP VCO n Lock Detection Rev. 1.3 RATESEL DSQLCH DOUT+ Retime DOUT– ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5013 specifications are guaranteed when using the recommended application circuit (including component tolerance) of "Typical Application Schematic" on page 12. ...
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... Si5013 DOUT CLK OUT DOUT, CLKOUT Figure 3. DOUT and CLKOUT Rise/Fall Times RESET/Cal LOL DATAIN LOL Cf-D C r-D Figure 2. Clock to Data Timing Figure 4. PLL Acquisition Time Rev. 1.3 80% 20% ...
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... DATAIN LOS Figure 5. LOS Response LOS Threshold Level t LOS Rev. 1.3 Si5013 7 ...
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... Si5013 Table 2. DC Characteristics (V = 3.3 V ±5 – ° Parameter 1 Supply Current OC-12 OC-3 Power Dissipation OC-12 OC-3 Common Mode Input Voltage (DIN) Common Mode Input Voltage (REFCLK) DIN Single-ended Input Voltage Swing DIN Differential Input Voltage Swing REFCLK Single-ended Input Voltage Swing ...
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... MHz V SLICE_LVL = 750 mV to SLICE 2.25 V SLICE_LVL = 750 LOS_LVL = 1.50 to 2.50 V LOS t Figure 5 on page 7 LOS V = (LOS_LVL – 1.50)/25. LOS Rev. 1.3 Si5013 Min Typ Max Unit .154 — 666 MHz — 125 155 ps — 125 155 ps ...
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... Si5013 Table 4. AC Characteristics (PLL Characteristics 3.3 V ±5 – ° Parameter Jitter Tolerance * (OC-12 Mode) Jitter Tolerance * (OC-3 Mode) * RMS Jitter Generation * Peak-to-Peak Jitter Generation * Jitter Transfer Bandwidth * Jitter Transfer Peaking Acquisition Time—OC-12 (Reference clock applied) Acquisition Time—OC-12 (Reference-less operation) ...
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... Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol Value V –0 –0.3 to 3.6 DIG V –0 DIF DD ±50 T –55 to 150 JCT T –55 to 150 STG 1 Symbol Test Condition ϕ Still Air JA Rev. 1.3 Si5013 Unit 0. °C °C kV Value Unit 38 °C/W 11 ...
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... Clock (Optional) Loss-of-Signal Level Set 12 BER Alarm LVTTL Loss-of-Signal Indicator Control Inputs Loss-of-Lock Indicator DIN+ DIN– Si5013 REFCLK+ CLKOUT+ REFCLK– CLKOUT– 100 VDD 10 kΩ 0.1 µF Data Slice Level Set Bit Error Rate Level Set Rev. 1.3 ...
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... PLL the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the Si5013 uses the reference clock to center the VCO output frequency so that clock and data is recovered from the input data stream. The device self configures for operation with one of three reference clock frequencies ...
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... This produces a stable output clock as long as supply and temperature are constant. 14 Loss-of-Signal The Si5013 indicates a loss-of-signal condition on the LOS output pin when the input peak-to-peak signal level on DIN falls below an externally controlled threshold. The LOS threshold range is specified in Table 3 on page 9 and is set by applying a voltage on the LOS_LVL pin ...
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... SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. Jitter Tolerance The Si5013’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 8. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device ...
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... Device Grounding The Si5013 uses the GND pad on the bottom of the 28- pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figure 15 on page 19 and Figure 16 on page 23 for the ground (GND) pad location ...
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... RFCLK+ 10 kΩ 2.5 kΩ RFCLK– 10 kΩ GND Si5013 2.5 V (±5%) DIN+ 50 Ω 5 kΩ 50 Ω 7.5 kΩ DIN– GND Si5013 2.5 V (±5%) 2.5 kΩ RFCLK + 10 kΩ 2.5 kΩ RFCLK – 10 kΩ GND Rev. 1.3 Si5013 17 ...
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... Figure 13. Single-Ended Input Termination for DIN (ac coupled) Differential Output Circuitry The Si5013 utilizes a current-mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 on page 8 ...
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... DOUT– TDI LOL Figure 15. Si5013 Pin Configuration Table 8. Si5013 Pin Descriptions I/O Signal Level I LVTTL Data Rate Select. This pin configures the onboard PLL for clock and data recovery at one of two user selectable data rates. See Table 7 for configuration settings. ...
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... Si5013 Table 8. Si5013 Pin Descriptions (Continued) Pin # Pin Name 7 LOL 8 LTR 9 LOS 10 DSQLCH 11,14,18,21, VDD 25 12 DIN+ 13 DIN– 15 GND 16 DOUT– 17 DOUT+ 19 RESET/CAL 20 I/O Signal Level O LVTTL Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 10 ...
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... Table 8. Si5013 Pin Descriptions (Continued) Pin # Pin Name 20 REXT 22 CLKOUT– 23 CLKOUT+ 24 CLKDSBL 26 BER_LVL 27 BER_ALM 28 NC GND Pad, 2 GND I/O Signal Level External Bias Resistor. This resistor is used to establish internal bias cur- rents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. ...
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... Si5013 Ordering Guide Part Number Si5013-BM 22 Package Voltage 28-lead MLP 3.3 Rev. 1.3 Temperature – °C ...
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... Package Outline Figure 16 illustrates the package details for the Si5013. Table 9 lists the values for the dimensions shown in the illustration D TOP VIEW Figure 16. 28-Lead Micro Leaded Package (MLP θ SEATING PLANE SECTION "C–C" e SCALE: NONE Table 9. Package Diagram Dimensions ...
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... Si5013 Document Change List Revision 0.2 to Revision 1.0 ! Added Figure 4, “PLL Acquisition Time,” on page 6. ! Table 2 on page 8 Updated values: Supply Current " Updated values: Power Dissipation " Updated values: Common Mode Input Voltage " (REFCLK) Updated values: Output Common Mode Voltage " ...
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... Notes: Rev. 1.3 Si5013 25 ...
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... Si5013 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...