ICS932S200BFLFT IDT, Integrated Device Technology Inc, ICS932S200BFLFT Datasheet - Page 2

• Manufacturer Part Number: ICS932S200BFLFT
• Description: IC FREQ TIMING GENERATOR 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS932S200BFLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 133MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 133MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 932S200BFLFT

0427D—12/15/08
ICS932S200
Pin Descriptions
20, 21, 24, 29,
38, 40, 44, 48,
22, 23, 27, 31,
43, 47, 51, 56
1, 7, 8, 13, 19
4,. 10, 16, 17,
Pin number
18, 15, 14,
50, 49, 46,
55, 54, 53
45, 42, 41
26, 25
33, 32
12, 11
3, 2
28
30
34
35
36
37
52
39
5
6
9
GND
REF(1:0)
VDD
X1
X2
PCICLK_F
PCICLK (4:0)
3V66 (1:0)
SEL 133/100#
48MHz
SEL (1:0)
SPREAD#
PD#
CPU_STOP#
PCI_STOP#
VDDL
CPUCLK (5:0)
IOAPIC (2:0)
Pin name
PWR
OUT
PWR
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
PWR
OUT
OUT
Type
Gnd pins
14.318MHz reference clock outputs at 3.3V
Power pins 3.3V
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
Free running PCI clock not affected by PCI_STOP#
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is
driven active..
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
Fixed 48MHz clock output. 3.3V
Function select pins. See truth table for details.
Enables spread spectrum when active(Low). modulates all the CPU, PCI,
IOAPIC and 3V66 clocks. Does not affect the REF and 48MHz clocks.
0.5% down spread modulation.
This asynchronous input powers down the chip when drive active(Low).
The internal PLLs are disabled and all the output clocks are held at a Low
state.
This asychronous input halts the CPUCLK and the 3V66 clocks at logic "0"
when driven active(Low).
This asynchronous input halts the PCICLK at logic"0" when driven
active(Low). PCICLK_F is not affected by this input.
Power pins 2.5V
Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state
of the SEL 133/100MHz.
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at
16.67MHz.
2
Description