IDTCV145NLG IDT, Integrated Device Technology Inc, IDTCV145NLG Datasheet - Page 3

• Manufacturer Part Number: IDTCV145NLG
• Description: IC CLK BUFFER 1-19 DIFF 72VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of IDTCV145NLG

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 72-VFQFN, 72-VFQFPN
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV145NLG

PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
IDTCV145
1-TO-19 DIFFERENTIAL CLOCK BUFFER
Symbol
V
V
T
T
T
ESD Prot
DIF_[16:0] & DIF_[16:0]#
DDIN
STG
AMBIENT
CASE
DDA
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
SA_2/PLL_BYPASS#
CLK_IN, CLK_IN#
DIF & DIF# [18:17]
OE _17_18#
HIGH_BW#
OE_01234#
OE_[16:5]#
Pin Name
SA_[1:0]
FS_A
IREF
SDA
SCL
PD#
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
Description
I/O, OC
Type
OUT
OUT
I N
I N
I N
I N
I N
I N
I N
I N
I N
I N
I N
Min.
2000
–65
26, 30, 31, 33, 34, 38, 39,
41, 42, 44, 45, 49, 50, 52,
21, 24, 29, 32, 37, 40, 43,
53, 55, 56, 58, 59, 61, 62
0
6 - 9, 12 - 17, 22, 23, 25,
48, 51, 54, 57, 60
65 - 68
70, 71
35, 36
Pin #
69
18
19
20
72
4
1
5
3
Max.
+150
+115
+70
4.6
4.6
(1)
Unit
°C
°C
°C
V
V
V
0.7v Differential input
0.7 V Differential clock outputs, geared to a ratio of the input clock
0.7 V Differential clock outputs, which can be configured to be 1:1 instead of geared. Default
is geared same as 0-9 outputs.
3.3 V LVTTL active LOW input for enabling corresponding differential output clock. Clocks
3.3 V LVTTL active low input for enabling both DIF10 and 11differential output clocks. Clocks
also can be disabled via SMBus registers individually.
3.3V LVTTL input
3.3 V LVTTL input for selecting the PLL bandwidth. 0 = HIGH BW, 1 = LOW BW.
SMBus slave clock input
Open collector SMBus data
A precision resistor is attached to this pin to set the differential output current
3.3V LVTTL input selecting the address. SA_[2:0] set device SMBus address.
3.3 V LVTTL input for PLLbypass and SMBus address
3.3V LVTTL input to establish a HIGH (>200Mhz) or LOW frequency(<200Mhz) range
3.3 V LVTTL input to power up or power down the device (see PD Functionality table).
3
also can be disabled via SMBus registers
OE FUNCTIONALITY
PD FUNCTIONALITY
PD# / V
3.3V (Nom)
OE# - Pin
GND
0
0
1
1
DDA
Inputs
CLK_IN / CLK_IN#
OE# - SMBus bit
Running
Description
X
1
0
1
0
COMMERCIAL TEMPERATURE RANGE
DIF
Outputs
Running
Normal
Tristate
Tristate
Tristate
Hi-Z
DIF
DIF#
PLL State
DIFF]#
Normal
Tristate
Tristate
Tristate
OFF
O N