ICS9EMS9633BKLFT IDT, Integrated Device Technology Inc, ICS9EMS9633BKLFT Datasheet - Page 2

• Manufacturer Part Number: ICS9EMS9633BKLFT
• Description: IC EMBEDDED PC MAIN CLK 48VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9EMS9633BKLFT

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 48-MLF
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SSOP Pin Description
IDT
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9EMS9633
ULTRA MOBILE PC CLOCK FOR EMBEDDED APPLICATIONS
1
2
3
4
5
6
7
8
9
TM
/ICS
REF
GNDREF
VDDCORE_3.3
FSC_L
TEST_MODE
TEST_SEL
SCLK
SDATA
VDDCORE_3.3
VDDIO_1.5
DOT96C_LPR
DOT96T_LPR
GNDDOT
GNDLCD
LCD100C_LPR
LCD100T_LPR
VDDIO_1.5
VDDCORE_3.3
*CR#0
GNDSRC
SRCC0_LPR
SRCT0_LPR
*CR#1
VDDCORE_3.3
TM
Ultra Mobile PC Clock for Embedded Applications
PIN NAME
TYPE
PWR Ground pin for the REF outputs.
PWR 3.3V power for the PLL core
PWR 3.3V power for the PLL core
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR Ground pin for DOT clock output
PWR Ground pin for LCD clock output
PWR Power supply for low power differential outputs, nominal 1.5V.
PWR 3.3V power for the PLL core
PWR Ground pin for the SRC outputs
PWR 3.3V power for the PLL core
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
14.318 MHz reference clock.
Low threshold input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode
while in test mode. Refer to Test Clarification Table.
TEST_SEL: latched input to select TEST MODE
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm resistor
to GND needed. No Rs needed.
Complement clock of low power differential pair for LCD100 SS clock. No 50ohm
resistor to GND needed. No Rs needed.
True clock of low power differential pair for LCD100 SS clock. No 50ohm resistor to
GND needed. No Rs needed.
Clock request for SRC0, 0 = enable, 1 = disable
Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
Clock request for SRC1, 0 = enable, 1 = disable
1 = All outputs are tri-stated for test
0 = All outputs behave normally.
2
DESCRIPTION
Datasheet
1617—08/19/09