ICS952001AFT IDT, Integrated Device Technology Inc, ICS952001AFT Datasheet

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ICS952001AFT

Manufacturer Part Number
ICS952001AFT
Description
IC TIMING CTRL HUB P4 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Timing Control Hubr
Datasheet

Specifications of ICS952001AFT

Input
Crystal
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
952001AFT
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
Features/Benefits:
Key Specifications:
Functionality
Note: For additional margin testing frequencies, refer to Byte 4
952001 Rev A 01/24/02
B i t 2 B i t 7 B i t 6 B i t 5 B i t 4
F S 4 F S 3 F S 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2 - Pairs of differential CPUCLKs (differential current mode)
1 - SDRAM @ 3.3V
8 - PCI @3.3V
2 - AGP @ 3.3V
2 - ZCLKs @ 3.3V
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
(Default is 24MHz)
3- REF @3.3V, 14.318MHz.
Programmable output frequency, divider ratios, output
rise/falltime, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
operations.
For PC133 SDRAM system use the ICS9179-06 as the
memory buffer.
For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
Uses external 14.318MHz crystal.
PCI - PCI output skew: < 500ps
CPU - SDRAM output skew: < 1ns
AGP - AGP output skew: <150ps
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Integrated
Circuit
Systems, Inc.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
C Index read/write and block read/write
F S 1 F S 0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1 0 0 . 0 0
1 0 0 . 0 0
1 0 0 . 0 0
1 0 0 . 0 0
1 0 0 . 0 0
1 0 0 . 0 0
1 0 0 . 0 0
1 0 0 . 0 0
1 0 0 . 0 0
1 0 0 . 0 0
(M H z )
6 6 . 6 7
8 0 . 0 0
8 0 . 0 0
9 5 . 0 0
9 5 . 0 0
6 6 . 6 7
C P U
S D R A M
1 0 0 . 0 0
2 0 0 . 0 0
1 3 3 . 3 3
1 5 0 . 0 0
1 2 5 . 0 0
1 6 0 . 0 0
1 3 3 . 3 3
2 0 0 . 0 0
1 6 6 . 6 7
1 6 6 . 6 7
1 3 3 . 3 3
1 3 3 . 3 3
1 2 6 . 6 7
(M H z )
6 6 . 6 7
9 5 . 0 0
6 6 . 6 7
2
C
(M H z )
Z C L K
6 6 . 6 7
6 6 . 6 7
6 6 . 6 7
6 6 . 6 7
6 0 . 0 0
6 2 . 5 0
6 6 . 6 7
8 0 . 0 0
6 6 . 6 7
6 2 . 5 0
7 1 . 4 3
6 6 . 6 7
6 6 . 6 7
6 3 . 3 3
6 3 . 3 3
5 0 . 0 0
( M H z )
6 6 . 6 7
6 6 . 6 7
6 6 . 6 7
6 6 . 6 7
6 0 . 0 0
6 2 . 5 0
6 6 . 6 7
6 6 . 6 7
6 6 . 6 7
6 2 . 5 0
8 3 . 3 3
6 6 . 6 7
6 6 . 6 7
6 3 . 3 3
6 3 . 3 3
5 0 . 0 0
A G P
PD#/Vtt_PWRGD
CPU_STOP#
PCI_STOP#
MULTISEL
** These inputs have a 120K pull down to GND.
**FS3/PCICLK_F0
**FS4/PCICLK_F1
* These inputs have a 120K pull up to VDD.
FS (4:0)
SDATA
48-Pin 300-mil SSOP and TSSOP
SCLK
*PCI_STOP#
PD#
**
*
**FS2/REF2
*FS1/REF1
X2
X1
FS0/REF0
GNDREF
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDDREF
GNDPCI
GNDPCI
VDDPCI
VDDPCI
ZCLK0
ZCLK1
GNDZ
VDDZ
Pin Configuration
X1
X2
XTAL
OSC
Spectrum
PLL2
Spread
Control
Config.
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
PLL1
Logic
Reg.
Block Diagram
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
DIVDER
DIVDER
DIVDER
DIVDER
ZCLK
CPU
AGP
PCI
/ 2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Stop
Stop
VDDSD
SDRAM
GNDSD
CPU_STOP#
CPUCLKT_1
CPUCLKC_1
VDDCPU
GNDCPU
CPUCLKT_0
CPUCLKC_0
IREF
GNDA
VDDA
SCLK
SDATA
PD#*/Vtt_PWRGD
GNDAGP
AGPCLK0
AGPCLK1
VDDAGP
VDDA48
48MHz
24_48MHz/MULTISEL
GND48
2
2
6
2
2
2
2
48MHz
24_48MHz
CPUCLKT (1:0)
CPUCLKC (1:0)
ZCLK (1:0)
PCICLK (9:0)
PCICLK_F (1:0)
AGP (1:0)
REF (1:0)
*
I REF
*

Related parts for ICS952001AFT

ICS952001AFT Summary of contents

Page 1

Integrated Circuit Systems, Inc. Recommended Application: SIS 645/650 style chipsets. Output Features: • Pairs of differential CPUCLKs (differential current mode) • SDRAM @ 3.3V • PCI @3.3V • AGP @ 3.3V • ...

Page 2

Integrated Circuit Systems, Inc. General Description The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR ...

Page 3

Integrated Circuit Systems, Inc. CPUCLK Swing Select Functions ...

Page 4

Integrated Circuit Systems, Inc. 2 General I C serial interface information for the ICS952001 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 • ICS clock will acknowledge • Controller (host) ...

Page 5

Integrated Circuit Systems, Inc. Serial Configuration Command Bitmap Bytes 0-3: Are reserved for external clock buffer. Byte4: Functionality and Frequency Select Register (default = ...

Page 6

Integrated Circuit Systems, Inc. Byte 5: Control Register (1 = enable disable ...

Page 7

Integrated Circuit Systems, Inc. Byte 9: Watchdog Timer Count Register ...

Page 8

Integrated Circuit Systems, Inc. Byte 13: Spread Spectrum Control Register ...

Page 9

Integrated Circuit Systems, Inc. Byte 17: Output Divider Control Register ...

Page 10

Integrated Circuit Systems, Inc. Byte 20: Group Skew Control Register Byte 21: Slew Rate Control Register ...

Page 11

Integrated Circuit Systems, Inc. Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . ...

Page 12

Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 70C 2.5 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP2B 1 Output Impedance R DSN2B Output High Voltage V OH2B Output Low ...

Page 13

Integrated Circuit Systems, Inc. Electrical Characteristics - 24M, 48M, REF 70C 3.3 V +/-5 DDL PARAMETER SYMBOL 1 Output Impedance R DSP5 1 Output Impedance R DSN5 Output High ...

Page 14

Integrated Circuit Systems, Inc. Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on ...

Page 15

Integrated Circuit Systems, Inc. PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next high to low ...

Page 16

Integrated Circuit Systems, Inc INDEX INDEX AREA AREA 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C Ordering Information ICS952001yFT Example: ICS XXXX ...

Page 17

Integrated Circuit Systems, Inc. Ordering Information ICS952001yFT Example: ICS XXXX PPP Pattern Number ( digit number for parts with ROM code patterns) Package Type Revision Designator Device Type (consists digit numbers) ...

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