ICS9DB823BGLFT IDT, Integrated Device Technology Inc, ICS9DB823BGLFT Datasheet - Page 6

• Manufacturer Part Number: ICS9DB823BGLFT
• Description: IC PC CLOCK 3.3V 48-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of ICS9DB823BGLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB823BGLFT

Pin Description for OE_INV = 1
IDT
PIN #
9DB823B
Eight Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
®
Eight Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
GND
PD#
DIF_STOP
HIGH_BW#
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OE5#
OE6#
DIF_6#
DIF_6
VDD
OE_INV
DIF_7#
DIF_7
OE4#
OE7#
LOCK
IREF
GNDA
VDDA
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
Ground pin.
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
Active High input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
3.3V output indicating PLL Lock Status. This pin goes high when lock is
achieved.
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
6
DESCRIPTION
1444D - 08/31/10