ICS9FG1200DF-1LFT IDT, Integrated Device Technology Inc, ICS9FG1200DF-1LFT Datasheet
ICS9FG1200DF-1LFT
Specifications of ICS9FG1200DF-1LFT
Related parts for ICS9FG1200DF-1LFT
ICS9FG1200DF-1LFT Summary of contents
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Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Description ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCIe Gen2, or Fully Buffered DIMM applications. The outputs are configured ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Pin Configuration Power Groups Pin Number VDD GND 56 55 11,22,38,50 12,23,37,49 Functionality at Power Up (PLL Mode) CLK_IN (CPU FSB) 1 FS_A_410 MHz 1 100 <= CLK_IN < ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Pin Description PIN # PIN NAME 1 HIGH_BW# 2 CLK_IN 3 CLK_IN# 4 SMB_A0 5 OE0# 6 DIF_0 7 DIF_0# 8 OE1# 9 DIF_1 10 DIF_1# 11 VDD 12 ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Pin Description (continued) PIN # PIN NAME 29 SMBCLK 30 SMB_A2_PLLBYP# 31 OE6# 32 DIF_6# 33 DIF_6 34 OE7# 35 DIF_7# 36 DIF_7 37 GND 38 VDD 39 DIF_8# ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 9FG1200-1 Programmable Gear Ratios CLK_IN Geared DIF (CPU FSB) Outputs MHz MHz M 100.00 133.33 3 100.00 166.67 3 100.00 200.00 1 100.00 266.67 3 100.00 333.33 3 100.00 ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 9FG1200-1 1:1 PLL Programming Byte 8, Byte 8, Byte 8, bit 2 bit 1 bit 0 FSC FSB FS_A_410 ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Core Supply Voltage VDD_A 3.3V Logic Supply Voltage VDD_In Storage Temperature Ambient Operating Temp Tambient Case Temperature Tcase Input ESD protection ESD prot ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Electrical Characteristics - DIF 0.7V Current Mode Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Current Source Output Impedance ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Electrical Characteristics - Skew and Differential Jitter Parameters 70°C; Supply Voltage V = 3.3 V +/- Group Parameter t CLK_IN, DIF[x:0] SPO_PLL t ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Electrical Characteristics - Phase Jitter PARAMETER SYMBOL t jphPCIe1 t jphPCIe2Lo Jitter, Phase t jphPCIe2Hi t jphFBD1_3.2G t jphFBD1_4.8G Notes on Phase Jitter: 1 See http://www.pcisig.com for complete specs. ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD ® IDT 9FG1200 SMBus Address Mapping when using CK410B+ and DB400/800 SMB_A(2:0) = 000 SMB Adr: D0 9FG1200 (DB1200G) ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD General SMBus serial interface information for the 9FG1200D-1 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D0 • ICS clock ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: Gear Ratio Select Register Byte 0 Pin # Name DIF(9:0) Group of 10 gear ratio enable Bit 7 DIF(11:10) Group of 2 gear ratio enable Bit 6 - ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: Output Enable Readback Register Byte 4 Pin # Name 46 Bit 7 Bit 6 1 Bit 5 30 Readback - SMB_A2_PLLBYP# In Bit 4 Bit 3 Bit 2 ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: 1:1 PLL Frequency Selection Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 - Bit 2 - Bit 1 - Bit 0 ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBus Table: Gear PLL Frequency Control Register Byte 12 Pin # Name Bit 7 - Gear PLL N Div7 Bit 6 - Gear PLL N Div6 Bit 5 - ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: Reserved Register Byte 16 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: 1:1 PLL Frequency ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: Reserved Register Byte 20 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Test Byte Register Byte ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Alternative termination for LVDS and other common differential signals. Vdiff Vp-p Vcm 0.45 v 0.22v 1.08 0.58 0.6 0.28 0.80 0.40 0.6 0.60 0.3 1.2 R1a = R1b = ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD INDEX INDEX AREA AREA 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C Frequency Gearing ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD INDEX INDEX AREA AREA aaa Ordering Information Part / Order Number Shipping Packaging 9FG1200DF-1LF 9FG1200DF-1LFT Tape ...
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ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Revision History A 12/11/2007 Final Release. B 1/21/2009 Update Skew and Phase Jitter tables. C 2/8/2010 Updated part ordering information Innovate with IDT and accelerate your future networks. Contact: ...