ics9fg1201 Integrated Device Technology, ics9fg1201 Datasheet

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ics9fg1201

Manufacturer Part Number
ics9fg1201
Description
Frequency Generator For P4tm Cpu, Pci-express* & Fully Buffered Dimm Clocks
Manufacturer
Integrated Device Technology
Datasheet

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Frequency Generator for CPU, PCIe Gen1* & Fully Buffered
DIMM Clocks
Description
ICS9FG1201 follows the Intel DB1200G Differential Buffer
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCI Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410 or CK410B main clock generator,
such as the ICS954101 or ICS932S401, drives the ICS9FG1201.
ICS9FG1201 can provide outputs up to 400MHz.
Key Specifications
Funtional Block Diagram
IDT
TM
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps within a group
DIF output-to-output skew < 100ps across all outputs
56-pin SSOP/TSSOP package
Available in RoHS compliant packaging
/ICS
TM
Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CLK_IN
CLK_IN#
OE#
OE(9:0)#
10
CONTROL
LOGIC
COMPATIBLE
COMPATIBLE
SPREAD
SPREAD
PLL
PLL
1
LOGIC
LOGIC
SHIFT
SHIFT
Features/Benefits
GEAR
GEAR
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(11:10) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
LOGIC
LOGIC
STOP
STOP
10
2
IREF
DIF(11:10)
DIF(9:0)
ICS9FG1201H
DATASHEET
1371C — 02/12/08

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ics9fg1201 Summary of contents

Page 1

... Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410 or CK410B main clock generator, such as the ICS954101 or ICS932S401, drives the ICS9FG1201. ICS9FG1201 can provide outputs up to 400MHz. Key Specifications • ...

Page 2

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Pin Configuration Functionality Table CLK_IN (CPU FSB) 1 FS_A_410 MHz 1 100.00 1 133.33 1 166. 200.00 0 266.66 0 333.33 0 400.00 1. FS_A_410 is a low-threshold input. Please see the V specifications in the Input/Supply/Common Output Parameters Table for correct values. ...

Page 3

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Power Groups Pin Number VDD GND 56 55 Main PLL, Analog 11,22,38,50 12,23,37,49 Pin Description Pin # Pin Name 1 HIGH_BW# 2 CLK_IN 3 CLK_IN# 4 SMB_A0 5 OE0# 6 DIF_0 7 DIF_0# 8 OE1# 9 DIF_1 10 DIF_1# 11 VDD 12 GND 13 DIF_2 14 DIF_2# ...

Page 4

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Pin Description (continued) Pin # Pin Name 29 SMBCLK 30 SMB_A2_PLLBYP# 31 OE6# 32 DIF_6# 33 DIF_6 34 OE7# 35 DIF_7# 36 DIF_7 37 GND 38 VDD 39 DIF_8# 40 DIF_8 41 OE8# 42 DIF_9# 43 DIF_9 44 OE9# 45 VTT_PWRGD#/PD 46 FS_A_410 47 DIF_10# 48 DIF_10 49 GND 50 VDD ...

Page 5

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks ICS9FG1201 Programmable Gear Ratios SMBus Byte 0 Input Output (m) ( ...

Page 6

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks TM TM IDT /ICS 9FG1201 SMBus A ddress M apping when using CK410/CK 410B and DB400/800 SMB_A(2:0) = 000 SMB Adr: D0 9FG1201 ...

Page 7

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks General SMBus serial interface information for the ICS9FG1201H How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D0 • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ...

Page 8

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks SMBusTable: Gear Ratio Select Register Byte 0 Pin # Name Bit 7 DIF(9:0) Group of 10 gear ratio enable Bit 6 DIF(11:10) Group of 2 gear ratio enable - Bit 5 Bit 4 - Gear Ratio FS4 (FS_A_410) - Bit 3 ...

Page 9

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks SMBusTable: Output Enable Readback Register Byte 4 Pin # Name Bit 7 46 Bit 6 1 Readback - HIGH_BW Readback - SMB_A2_PLLBYP# In Bit 5 Bit 4 Bit 3 Bit 2 53 Readback - OE10_11# Input Bit 1 44 Bit 0 41 SMBusTable: Vendor & ...

Page 10

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks SMBusTable: 1:1 PLL Frequency Selection Byte 8 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 - Bit 1 - Bit 0 - SMBusTable: Reserved Register Byte 9 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ...

Page 11

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks SMBus Table: Gear PLL Frequency Control Register Byte 12 Pin # Name - Gear PLL N Div7 Bit 7 - Gear PLL N Div6 Bit 6 - Gear PLL N Div5 Bit 5 - Gear PLL N Div4 Bit 4 - Gear PLL N Div3 ...

Page 12

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks SMBusTable: Reserved Register Byte 16 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: 1:1 PLL Frequency Control Register Byte 17 Pin # Name Bit 7 Bit 6 Bit 5 - 1:1 PLL M Div5 Bit 4 ...

Page 13

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks SMBusTable: Reserved Register Byte 20 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBusTable: Test Byte Register Byte 21 Test Bit 7 ` Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Note: Do NOT write to Bit 21. Erratic device operation will result! Frequency Generator for CPU, PCIe Gen1* & ...

Page 14

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Absolute Max PARAMETER SYMBOL 3.3V Core Supply Voltage VDD_A 3.3V Logic Supply Voltage VDD_In Storage Temperature Ambient Operating Temp Tambient Case Temperature Tcase Input ESD protection ESD prot Electrical Characteristics - Input/Supply/Common Output Parameters 70° ...

Page 15

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Electrical Characteristics - DIF 0.7V Current Mode Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Current Source Output Zo Impedance Voltage High VHigh Voltage Low VLow Max Voltage Vovs Min Voltage ...

Page 16

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Electrical Characteristics - Skew and Differential Jitter Parameters 70°C; Supply Voltage V = 3.3 V +/- Group Parameter CLK_IN, DIF[x:0] t SPO_PLL CLK_IN, DIF[x:0] t PD_BYP DIF[11:10] t SKEW_G2 DIF[9:0] t SKEW_G10 Output-to-Output Skew across all 12 outputs (Common to ...

Page 17

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. ...

Page 18

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Alternative termination for LVDS and other common differential signals. Vdiff Vp-p Vcm 0.45 v 0.22v 1.08 0.58 0.6 0.28 0.80 0.40 0.6 0.60 1.2 0.3 R1a = R1b = R1 Figure_3. L1 L1’ HSCL Output Buffer R2a = R2b = R2 Cable connected AC coupled application, figure 4 Component Value R5a,R5b 8 ...

Page 19

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks INDEX INDEX AREA AREA 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C Ordering Information ICS 9FG1201HFLF-T Example: ICS XXXX Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks ...

Page 20

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks INDEX INDEX AREA AREA Ordering Information ICS 9FG1201HGLF-T Example: ICS XXXX Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks ...

Page 21

... ICS9FG1201H Frequency Generator for CPU, PCIe Gen1* & Fully Buffered DIMM Clocks Revision History Rev. Issue Date Description A 10/22/07 Release to Final. Updated Key Specifications: B 01/29/08 Changed units for DIF output-to-output skew to "ps". C 02/12/08 Changed Cin value from pf. TM Innovate with IDT and accelerate your future networks. Contact: www ...

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