ICS950405AFLFT IDT, Integrated Device Technology Inc, ICS950405AFLFT Datasheet - Page 2

• Manufacturer Part Number: ICS950405AFLFT
• Description: IC SYSTEM CLK CHIP AMD-K8 48SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Timing Control Hubr

Specifications of ICS950405AFLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 300MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Frequency-max: 300MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 950405AFLFT

Pin Descriptions
ICS950405
0802F—04/22/05
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
PIN # PIN NAME
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
*FS0/REF0
VDDHTT
X1
X2
GND
*ModeA/HTTCLK0
*ModeB/PCICLK8/HTTCLK1
PCICLK9/HTTCLK2
VDDPCI
GND
PCICLK11/HTTCLK3
PCICLK10
PCICLK0
PCICLK1
GND
VDDPCI
PCICLK2
PCICLK3
VDDPCI
GND
2XPCICLK4
2XPCICLK5
2XPCICLK6
2XPCICLK7
SCLK
SDATA
GND
24_48MHz/Sel24_48#*
AVDD48
GND
48MHz/FS3**
PD#*
GND
GND
VDDCPU
CPUCLK8C1
CPUCLK8T1
VDDCPU
GND
CPUCLK8C0
CPUCLK8T0
GND
VDDA
Reset#
REF2/FS2*
VDDREF
GND
REF1/FS1*
TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
PIN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
Frequency select latch input pin / 14.318 MHz reference clock.
Supply for HTT clocks, nominal 3.3V.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Mode selection latch input pin / Hyper Transport output.
Mode selection latch input pin / PCI clock output / Hyper Transport output.
PCI clock output / Hyper Transport output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output / Hyper Transport output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
PCI clock output. This output is default @ 2X drive and can be programmed to lower drive
via IIC.
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
Ground pin.
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Ground pin.
Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin
Asynchronous active low input pin used to power down the device into a low power state.
The internal clocks are disabled and the VCO and the crystal are stopped.
Ground pin.
Ground pin.
Supply for CPU clocks, 3.3V nominal
Complimentary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Supply for CPU clocks, 3.3V nominal
Ground pin.
Complimentary clock of differential 3.3V push-pull K8 pair.
True clock of differential 3.3V push-pull K8 pair.
Ground pin.
3.3V power for the PLL core.
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
14.318 MHz reference clock / Frequency select latch input pin.
Ref, XTAL power supply, nominal 3.3V
Ground pin.
14.318 MHz reference clock / Frequency select latch input pin.
2
DESCRIPTION