ICS9FG104CGLFT IDT, Integrated Device Technology Inc, ICS9FG104CGLFT Datasheet - Page 8

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ICS9FG104CGLFT

Manufacturer Part Number
ICS9FG104CGLFT
Description
IC FREQ TIMING GENERATOR 28TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of ICS9FG104CGLFT

Input
*
Output
*
Frequency - Max
*
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Frequency-max
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1918-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS9FG104CGLFT
Manufacturer:
ICS
Quantity:
20 000
IDT
SMBus Table: PLL Frequency Control Register
SMBus Table: PLL Spread Spectrum Control Register
SMBus Table: PLL Spread Spectrum Control Register
SMBus Table: Reserved Test Register
Byte 11
Byte 12
Byte 13
Byte 14
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
TM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/ICS
TM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin #
Pin #
Pin #
Pin #
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved Test Register. Do not write to this register, erratic device operation may occur.
PLL N Div7
PLL N Div6
PLL N Div5
PLL N Div4
PLL N Div3
PLL N Div2
PLL N Div1
PLL N Div0
PLL SSP14
PLL SSP13
PLL SSP12
PLL SSP11
PLL SSP10
PLL SSP7
PLL SSP6
PLL SSP5
PLL SSP4
PLL SSP3
PLL SSP2
PLL SSP1
PLL SSP0
PLL SSP9
PLL SSP8
Name
Name
Name
Name
Byte11 bit(7:0) and Byte10
N Divider Programming
Programming bit(14:8)
Programming bit(7:0)
Control Function
Control Function
Control Function
Control Function
Spread Spectrum
Spread Spectrum
bit(7:6)
Reserved
8
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
and N Divider in Byte 11 and 12 will
Byte 0 Rom table. VCO Frequency
configure the PLL VCO frequency.
The decimal representation of M
Default at power up = latch-in or
Byte 13 and 14 will program the
Byte 13 and 14 will program the
These Spread Spectrum bits in
These Spread Spectrum bits in
= 14.318 x [NDiv(9:0)+8] /
spread pecentage of PLL
spread pecentage of PLL
0
0
0
0
[MDiv(5:0)+2]
1
1
1
1
0839O—12/03/08
PWD
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
0
0
0
0
0
0
0

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