ICS9FG104CGLFT IDT, Integrated Device Technology Inc, ICS9FG104CGLFT Datasheet - Page 7

• Manufacturer Part Number: ICS9FG104CGLFT
• Description: IC FREQ TIMING GENERATOR 28TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9FG104CGLFT

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1918-2

IDT
SMBus Table: Reserved Register
SMBus Table: Reserved Register
SMBus Table: M/N Programming Enable
SMBus Table: PLL Frequency Control Register
Byte 10
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Byte 7
Byte 8
Byte 9
TM
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/ICS
TM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin #
Pin #
Pin #
Pin #
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
REFOUT_En
M/N_Enable
PLL M Div5
PLL M Div4
PLL M Div3
PLL M Div2
PLL M Div1
PLL M Div0
PLL N Div8
PLL N Div9
Name
Name
Name
Name
M Divider Programming
N Divider Prog bit 8
N Divider Prog bit 9
Control Function
Control Function
Control Function
Control Function
M/N Prog. Enable
REFOUT Enable
bit (5:0)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
and N Divider in Byte 11 and 12 will
Byte 0 Rom table. VCO Frequency
configure the PLL VCO frequency.
The decimal representation of M
Default at power up = latch-in or
Disable
Disable
= 14.318 x [NDiv(9:0)+8] /
0
0
0
0
[MDiv(5:0)+2]
Enable
Enable
1
1
1
1
0839O—12/03/08
PWD
PWD
PWD
PWD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
X
X
X
X
X
X
X
X
0