ML610Q408-NNNTBZ03A7 Rohm Semiconductor, ML610Q408-NNNTBZ03A7 Datasheet - Page 306

• Manufacturer Part Number: ML610Q408-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 8CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q408-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 21 RC Oscillation Type A/D Converter
<First step>
Note:
From this point of time, the RC oscillator circuit (RCOSC0) continues oscillation for about 0.366 second with the
reference resistance RS0. Then, when Counter A overflows, the RADINT signal is set to “1” and an RC-ADC interrupt
RC-ADC interrupt request
CR oscillating
CNTA2–0
CNTB2–0
Base clock
CNTA1-0
CNTB1-0
(CROSC0)
In this example, nA0 is set to 4B0H because the gate time “nA0 x t
0.366 second. The value of nA0 is related to how much the margin of the quantization error of the A/D conversion is: the greater
the nA0 value is, the smaller the margin of error becomes.
To reduce noise contamination to the RC oscillator circuit caused by CPU operation, it is recommended to constantly put the
device into HALT mode during operation of RC oscillation.
RADMOD
(bits 4–0)
RADCON
BSCLK
RADINT
(bit 0)
HLT
state
Write “01H” in RADMOD to select Counter A reference mode and the oscillation mode that uses reference
resistance RS0.
Set the base clock to 32.768 kHz. (Write “00H” in FCON0.)
Preset “10000H – nA0” in Counter A.
Preset “0000H” in Counter B.
Write “01H” in RADCON to start A/D conversion operation.
Write “1” in the HLT bit of SBYCON to set the device to HALT mode.
Note) nA0=4B0H, t
Figure 21-14 Timing Chart for 1 Cycle of A/D Conversion (Example)
0FB50H
Stop
0000H
00H
32.768 kHz
SYSCLK
<First Step>
(Counter A reference mode)
=1/32768 Hz;
(Increments by BSCLK)
nA0·t
Oscillates with RS0
(Increments by
RCCLK (RS0))
BSCLK
01H (ERAD=1)
0.366 sec
=nB0·t
01H
to
RC CLK
: Software processing; (a) to (f): Hardware processing
(RS0)
21-16
(b)
(a)
Overflow
nB0
(c)
0000H
INT generated
00H
Stop
BSCLK
” in oscillation mode with reference resistor RS0 is set to
(Counter B reference mode)
nB0·tRCCLK(RT0)=nA1·t
10000H − nB0
Oscillates with RS0
(
(Increments by
RCCLK (RT0))
Increments by BSCLK
01H (ERAD=1)
<Second Step>
12H
)
BSCLK
Overflow
(d)
(e)
(f)
INT generated
nA1
00H
Stop
0000H