ML610Q408-NNNTBZ03A7 Rohm Semiconductor, ML610Q408-NNNTBZ03A7 Datasheet - Page 10

• Manufacturer Part Number: ML610Q408-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 8CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q408-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User’s Manual
Contents
Chapter 13
13.
Chapter 14
14. Port 0 ............................................................................................................................................................................. 14-1
Chapter 15
15. Port 2 ............................................................................................................................................................................. 15-1
13.1 Overview .................................................................................................................................................................... 13-1
13.2 Description of Registers ............................................................................................................................................. 13-2
13.3 Description of Operation .......................................................................................................................................... 13-11
13.4 Specifying port registers........................................................................................................................................... 13-20
14.1 Overview................................................................................................................................................................... 14-1
14.2 Description of Registers ............................................................................................................................................. 14-2
14.3 Description of Operation ............................................................................................................................................ 14-7
15.1 Overview................................................................................................................................................................... 15-1
SSIO1/ ”Slave mode” ................................................................................................................................................... 12-20
12.4.7 Functioning P56 (SOUT1: Output), P55 (SCK1: Input/Output), and P54 (SIN1: Input) as the SSIO1/
“Master mode”.............................................................................................................................................................. 12-21
12.4.8 Functioning P56 (SOUT1: Output), P55 (SCK1: Input/Output), and P54 (SIN1: Input) as the
SSIO1/ ”Slave mode” ................................................................................................................................................... 12-22
13.1.1 Features................................................................................................................................................................ 13-1
13.1.2 Configuration...................................................................................................................................................... 13-1
13.1.3 List of Pins.......................................................................................................................................................... 13-2
13.2.1 List of Registers .................................................................................................................................................. 13-2
13.2.2 UART0 Transmit/Receive Buffer (UA0BUF) .................................................................................................... 13-3
13.2.3 UART0 Control Register (UA0CON) ................................................................................................................ 13-4
13.2.4 UART0 Mode Register 0 (UA0MOD0) ............................................................................................................. 13-5
13.2.5 UART0 Mode Register 1 (UA0MOD1) ............................................................................................................. 13-6
13.2.6 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) ............................................................................ 13-8
13.2.7 UART0 Status Register (UA0STAT) ................................................................................................................ 13-9
13.3.1 Transfer Data Format...................................................................................................................................... 13-11
13.3.2 Baud rate......................................................................................................................................................... 13-12
13.3.3 Transmitted Data Direction............................................................................................................................. 13-13
13.3.4 Transmit Operation ......................................................................................................................................... 13-14
13.3.5 Receive Operation .......................................................................................................................................... 13-16
13.3.5.1 Detection of Start Bit........................................................................................................................................................ 13-18
13.3.5.2 Sampling Timing .............................................................................................................................................................. 13-18
12.3.5.3 Receive Margin ................................................................................................................................................................ 13-19
13.4.1 Functioning P43(TXD0) and P42(RXD0) as the UART ................................................................................ 13-20
13.4.2 Functioning P43(TXD0) and P02(RXD0) as the UART ................................................................................ 13-21
14.1.1 Features............................................................................................................................................................. 14-1
14.1.2 Configuration...................................................................................................................................................... 14-1
14.1.3 List of Pins.......................................................................................................................................................... 14-1
14.2.1 List of Registers .................................................................................................................................................. 14-2
14.2.2 Port 0 Data Register (P0D) ................................................................................................................................. 14-3
14.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1)............................................................................................ 14-4
14.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1) .................................................................... 14-5
14.2.5 External Interrupt Control Register 2 (EXICON2)............................................................................................. 14-6
14.3.1 External Interrupt / Secondary Function........................................................................................................... 14-7
14.3.2 Interrupt Request .............................................................................................................................................. 14-7
UART........................................................................................................................................................................... 13-1
Contents –5