ML610Q408-NNNTBZ03A7 Rohm Semiconductor, ML610Q408-NNNTBZ03A7 Datasheet - Page 126

• Manufacturer Part Number: ML610Q408-NNNTBZ03A7
• Description: MCU 8BIT 16K FLASH 8CH 100-TQFP
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of ML610Q408-NNNTBZ03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.25 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ML610Q407/ML610Q408/ML610Q409 User's Manual
Chapter 9 Timer
9.2.6
Address: 0F031H
Access: R/W
Access size: 8-bit
Initial value: 00H
TM0C is a special function register (SFR) that functions as an 8-bit binary counter.
When write operation to TM0C is performed, TM0C is set to “00H”. The data that is written is meaningless.
In 16-bit timer mode and 16-bit timer frequency measurement mode, if write operation is performed to either the
low-order TM0C or high-order TM1C, both the low-order and the high-order are set to “0000H”.
During timer operation, the TM0C content may not be read depending on the conditions of the timer clock and the
system clock.
Table 9-1 shows whether a TM0C read is enabled or disabled during timer operation for each condition of the timer
clock and system clock.
Initial value
External clock
Timer clock
TM0C
Timer 0 Counter Register (TM0C)
R/W
HTBCLK
HTBCLK
LSCLK
LSCLK
T0CK
T0C7
R/W
7
0
Table 9-1 TM0C Read Enable/Disable during Timer Operation
System clock
SYSCLK
HSCLK
HSCLK
HSCLK
LSCLK
LSCLK
LSCLK
T0C6
R/W
6
0
Read enabled.
Read enabled. However, to prevent the reading of undefined data
during incremental counting, read TM0C twice and check that the
results match.
Read disabled.
Read enabled.
Read disabled.
T0C5
R/W
5
0
9-8
T0C4
R/W
4
0
TM0C read enable/disable
T0C3
R/W
3
0
T0C2
R/W
2
0
T0C1
R/W
0
1
T0C0
R/W
0
0