PIC24FV32KA304-I/PT Microchip Technology, PIC24FV32KA304-I/PT Datasheet - Page 76

• Manufacturer Part Number: PIC24FV32KA304-I/PT
• Description: MCU 32KB FLASH 2KB RAM 44-TQFP
• Manufacturer: Microchip Technology

Specifications of PIC24FV32KA304-I/PT

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-44
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FV32KA304 FAMILY
7.2
The Reset times for various types of device Reset are
summarized in
signal, SYSRST, is released after the POR and PWRT
delay times expire.
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
TABLE 7-3:
DS39995B-page 76
POR
BOR
All Others
Note 1:
Note:
Reset Type
(6)
2:
3:
4:
5:
6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with
Device Reset Times
T
T
T
T
T
oscillator clock to the system.
FRC, and in such cases, FRC start-up time is valid.
For detailed operating frequency and timing specifications, see
OST
POR
PWRT
FRC
LOCK
Table
and T
= Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing
= Power-on Reset delay.
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time.
= 64 ms nominal if the Power-up Timer is enabled; otherwise, it is zero.
EC
FRC, FRCDIV
LPRC
ECPLL
FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
EC
FRC, FRCDIV
LPRC
ECPLL
FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
7-3. Note that the system Reset
LPRC
= RC Oscillator start-up times.
Clock Source
SYSRST Delay
T
T
T
T
T
T
T
POR
POR
POR
POR
POR
POR
POR
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
T
T
T
T
T
T
T
PWRT
PWRT
PWRT
PWRT
PWRT
PWRT
PWRT
+ T
+ T
+ T
+ T
+ T
+ T
+ T
—
PWRT
PWRT
PWRT
PWRT
PWRT
PWRT
PWRT
Section 29.0 “Electrical
System Clock
T
T
T
T
 2011 Microchip Technology Inc.
OST
FRC
FRC
FRC
T
T
T
T
Delay
T
T
T
T
LPRC
LOCK
LPRC
LOCK
+ T
+ T
OST
+ T
OST
+ T
—
FRC
—
FRC
—
LOCK
LOCK
LOCK
LOCK
Characteristics”.
1, 2
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 3, 4
1, 2, 5
1, 2, 4, 5
2
2, 3
2, 3
2, 4
2, 3, 4
2, 5
2, 3, 4
None
Notes