PIC24FV32KA304-I/PT Microchip Technology, PIC24FV32KA304-I/PT Datasheet - Page 175

• Manufacturer Part Number: PIC24FV32KA304-I/PT
• Description: MCU 32KB FLASH 2KB RAM 44-TQFP
• Manufacturer: Microchip Technology

Specifications of PIC24FV32KA304-I/PT

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-44
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.3
To compute the Baud Rate Generator (BRG) reload
value, use
EQUATION 17-1:
TABLE 17-1:
TABLE 17-2:
 2011 Microchip Technology Inc.
Note 1:
Note 1:
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
Note 1:
Address
Slave
2:
3:
Required
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
System
F
or
I2C1BRG
Setting Baud Rate When
Operating as a Bus Master
1 MHz
1 MHz
1 MHz
SCL
F
Equation
The address bits listed here will never cause an address match, independent of the address mask settings.
Address will be Acknowledged only if GCEN = 1.
Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
SCL
Based on F
Based on F
are disabled.
=
--------------------------------------------------------------------- -
I2C1BRG
R/W
Bit
I
I
0
1
x
x
x
x
x
x
2
2
=
C™ CLOCK RATES
C™ RESERVED ADDRESSES
17-1.


CY
COMPUTING BAUD RATE
RELOAD VALUE
----------- -
F
F
CY
SCL
CY
General Call Address
Start Byte
Cbus Address
Reserved
Reserved
HS Mode Master Code
Reserved
10-bit Slave Upper Byte
= F
= F
+ +
OSC
–
F
1
----------------------------- -
10 000 000
CY
OSC
/2; Doze mode and PLL

----------------------------- -
10 000 000
16 MHz
16 MHz
16 MHz
F
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
/2, Doze mode and PLL are disabled.

CY
F
F
CY

CY



(1)
–
(1)
1
(2)
(3)
PIC24FV32KA304 FAMILY
(Decimal)
(1)
157
78
39
37
18
13
9
4
6
3
I2C1BRG Value
17.4
The I2C1MSK register
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2C1MSK register causes the slave
module to respond, whether the corresponding
address bit value is ‘0’ or ‘1’. For example, when
I2C1MSK is set to ‘00100000’, the slave module will
detect both addresses: ‘0000000’ and ‘00100000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the IPMIEN bit (I2C1CON<11>).
Description
Note:
(Hexadecimal)
Slave Address Masking
As a result of changes in the I
the addresses in
and will not be Acknowledged in Slave
mode. This includes any address mask
settings
addresses.
9D
4E
27
25
12
D
9
4
6
3
that
(Register
include
Table 17-2
1.026 MHz
1.026 MHz
0.909 MHz
DS39995B-page 175
100 kHz
100 kHz
404 kHz
404 kHz
385 kHz
385 kHz
17-3) designates
Actual
99 kHz
F
any
SCL
are reserved
2
C protocol,
of
these