XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 47

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Clock Buffers and Networks
Table 59: Global Clock Switching Characteristics (Including BUFGCTRL)
Table 60: Input/Output Clock Switching Characteristics (BUFIO)
Table 61: Regional Clock Switching Characteristics (BUFR)
Table 62: Horizontal Clock Buffer Switching Characteristics (BUFH)
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
2.
Notes:
1.
T
T
T
Maximum Frequency
F
T
Maximum Frequency
F
T
T
T
Maximum Frequency
F
T
T
Maximum Frequency
F
BCCCK_CE
BCCCK_S
BCCKO_O
MAX
BIOCKO_O
MAX
BRCKO_O
BRCKO_O_BYP
BRDO_O
MAX
BHCKO_O
BHCCK_CE
MAX
T
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times
are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
T
The maximum input frequency to the BUFR is the BUFIO F
(1)
BCCCK_CE
BGCKO_O
/T
(2)
Symbol
Symbol
Symbol
Symbol
/T
/T
BCCKC_S
BCCKC_CE
BHCKC_CE
(BUFG delay from I0 to O) values are the same as T
and T
(1)
BCCKC_CE
(1)
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
CE pins Setup/Hold
S pins Setup/Hold
BUFGCTRL delay from I0/I1 to O
Global clock tree (BUFG)
Clock to out delay from I to O
I/O clock tree (BUFIO)
Clock to out delay from
I to O
Clock to out delay from I to O with Divide Bypass
attribute set
Propagation delay from CLR to O
Regional clock tree (BUFR)
BUFH delay from I to O
CE pin Setup and Hold
Horizontal clock buffer (BUFH)
Description
Description
Description
Description
www.xilinx.com
MAX
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
BCCKO_O
frequency.
values.
0.04/
0.11/
0.11/
0.14
0.56
0.28
0.10
0.04
0.00
0.00
0.07
0.69
800
800
800
500
-3
-3
-3
-3
0.04/
0.13/
0.13/
0.11
0.04
0.16
0.62
0.31
0.74
0.00
0.00
0.08
750
800
420
750
Speed Grade
Speed Grade
Speed Grade
Speed Grade
-2
-2
-2
-2
0.05/
0.16/
0.16/
0.13
0.05
0.18
0.73
0.36
0.80
0.00
0.00
0.10
700
710
300
700
-1
-1
-1
-1
0.04/
0.13/
0.13/
0.21
0.82
0.41
0.15
0.04
0.00
0.00
0.10
1.12
710
667
667
-1L
-1L
300
-1L
-1L
Units
Units
Units
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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