XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 32

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Table 47: Output Delay Measurement Methodology (Cont’d)
Input/Output Logic Switching Characteristics
Table 48: ILOGIC Switching Characteristics
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
2.
HT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVDCI/HSLVDCI, 2.5V
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
HSTL, Class III, with DCI
HSTL, Class I & II, 1.8V, with DCI
HSTL, Class III, 1.8V, with DCI
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
SSTL, Class I & II, 2.5V, with DCI
Setup/Hold
T
T
T
T
Combinatorial
T
T
Sequential Delays
T
T
T
T
T
Set/Reset
T
ICE1CK
ISRCK
IDOCK
IDOCKD
IDI
IDID
IDLO
IDLOD
ICKQ
RQ_ILOGIC
GSRQ_ILOGIC
RPW_ILOGIC
C
The value given is the differential output voltage.
REF
Symbol
/T
/T
/T
/T
ICKSR
IOCKD
is the capacitance of the probe, nominally 0 pF.
ICKCE1
IOCKDD
Description
CE1 pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IODELAY)
D pin to O pin propagation delay, no Delay
DDLY pin to O pin propagation delay (using IODELAY)
D pin to Q1 pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY)
CLK to Q outputs
SR pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR inputs
Description
www.xilinx.com
LDT_25
HSTL_III_DCI_18
LVPECL_25
LVDCI_25, HSLVDCI_25
LVDCI_18, HSLVDCI_18
LVDCI_15, HSLVDCI_15
HSTL_III_DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
SSTL2_I_DCI, SSTL2_II_DCI
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard
Attribute
–0.08
0.21/
0.66/
0.10/
0.07/
0.03
0.41
0.32
0.15
0.19
0.48
0.52
0.54
0.85
7.60
0.78
-3
–0.08
0.25/
0.78/
0.08/
0.12/
R
0.04
0.46
0.36
0.17
0.22
0.54
0.58
0.61
0.97
7.60
0.95
Speed Grade
100
100
()
1M
1M
1M
-2
50
50
50
50
50
50
REF
C
–0.08
10.51
(pF)
0.27/
0.96/
0.10/
0.14/
REF
0.04
0.54
0.42
0.20
0.25
0.64
0.68
0.70
1.15
1.20
-1
0
0
0
0
0
0
0
0
0
0
0
(1)
V
–0.11
10.51
0.31/
1.09/
0.11/
0.16/
0.05
0.64
0.50
0.23
0.28
0.73
0.78
0.93
1.32
1.30
V
V
V
V
1.25
0.75
-1L
MEAS
(V)
0
0
0.9
0.9
1.1
REF
REF
REF
REF
(2)
(2)
ns, Min
Units
V
0.75
1.25
(V)
0.6
1.5
0.9
1.8
0.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REF
0
0
0
0
32