XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 18

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XC6VSX475T-2FFG1759E

Manufacturer Part Number
XC6VSX475T-2FFG1759E
Description
IC FPGA VIRTEX 1759FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

Number Of Logic Elements/cells
476160
Number Of Labs/clbs
37200
Total Ram Bits
39223296
Number Of I /o
840
Number Of Gates
-
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1759-BBGA, FCBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
XC6VSX475T-2FFG1759I
XC6VSX475T-2FFG1759I

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Quantity
Price
Part Number:
XC6VSX475T-2FFG1759E
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Quantity:
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Part Number:
XC6VSX475T-2FFG1759E
Manufacturer:
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Quantity:
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Part Number:
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0
GTH Transceiver Switching Characteristics
Consult UG371:Virtex-6 FPGA GTH Transceivers User Guide for further information.
Table 32: GTH Transceiver Maximum Data Rate and PLL Frequency Range
Table 33: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Table 34: GTH Transceiver Reference Clock Switching Characteristics
X-Ref Target - Figure 5
DS152 (v3.2) April 1, 2011
Product Specification
Notes:
1.
F
F
F
F
F
F
T
T
T
T
T
Symbol
GTHMAX
GTHMIN
GPLLMAX
GPLLMIN
GTHDRPCLK
GCLK
RCLK
FCLK
DCREF
LOCK
PHASE
Symbol
Symbol
Lower data rates can be achieved using FPGA logic based oversampling designs.
Reference clock frequency range
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time
GTHDRPCLK maximum frequency
Maximum GTH transceiver data rate
Minimum GTH transceiver data rate
Maximum GTH PLL frequency
Minimum GTH PLL frequency
Description
80%
20%
Description
T
FCLK
Figure 5: Reference Clock Timing Parameters
Description
(1)
-1 speed grade
-2 and -3 speed grades
20% – 80%
80% – 20%
CLK
Initial PLL lock
Lock to data after PLL has locked
to the reference clock
T
www.xilinx.com
RCLK
PLL Output Divider = 1
PLL Output Divider = 4
PLL Output Divider = 1
PLL Output Divider = 4
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Conditions
Conditions
11.182
2.795
5.591
9.92
2.48
4.96
Min
150
150
-3
70
45
-3
All Speed Grades
ds152_05_042109
Speed Grade
Speed Grade
11.182
2.795
5.591
9.92
2.48
4.96
Typ
200
200
-2
50
70
-2
10.32
2.58
9.92
2.48
5.16
4.96
Max
645
700
-1
55
20
60
-1
2
Units
Units
Units
Gb/s
Gb/s
Gb/s
Gb/s
GHz
GHz
MHz
MHz
MHz
ms
ps
ps
µs
%
18

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