XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 21

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
Table 39: Maximum Performance for PCI Express Designs
System Monitor Analog-to-Digital Converter Specification
Table 40: Analog-to-Digital Specifications
DS152 (v3.2) April 1, 2011
Product Specification
F
F
F
AV
DC Accuracy: All external input channels. Both unipolar and bipolar modes.
Resolution
Integral Nonlinearity
Differential Nonlinearity
Unipolar Offset Error
Bipolar Offset Error
Gain Error
Bipolar Gain Error
Total Unadjusted Error
(Uncalibrated)
Total Unadjusted Error
(Calibrated)
Calibrated Gain Temperature
Coefficient
DC Common-Mode Reject
Conversion Rate
Conversion Time - Continuous
Conversion Time - Event
T/H Acquisition Time
DRP Clock Frequency
ADC Clock Frequency
CLK Duty cycle
PIPECLK
USERCLK
DRPCLK
DD
Symbol
= 2.5V ± 5%, V
Parameter
Pipe clock maximum frequency
User clock maximum frequency
DRP clock maximum frequency
(2)
(1)
(1)
REFP
(1)
= 1.25V, V
INL
DNL
TUE
TUE
CMRR
t
t
t
DCLK
ADCCLK
CONV
CONV
ACQ
Symbol
REFN
DC
Description
= 0V, ADCCLK = 5.2 MHz, T
No missing codes (T
Guaranteed Monotonic
Uncalibrated
Uncalibrated measured in bipolar mode
Uncalibrated - External Reference
Uncalibrated - Internal Reference
Uncalibrated - External Reference
Uncalibrated - Internal Reference
Deviation from ideal transfer function.
External 1.25V reference
Deviation from ideal transfer function.
Internal reference
Deviation from ideal transfer function.
External 1.25V reference
Variation of FS code with temperature
V
V
Number of CLK cycles
Number of CLK cycles
Number of CLK cycles
DRP clock frequency
Derived from DCLK
N
P
– V
= V
N
CM
=
=
Comments/Conditions
100mV
0.5V ± 0.5V,
www.xilinx.com
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
MIN
j
to T
= –40°C to 100°C, Typical values at T
MAX
)
250
500
250
-3
250
500
250
Speed Grade
Min
-2
10
26
40
–
–
–
–
–
–
–
–
–
–
–
–
–
–
4
8
1
±0.01
±0.2
±0.2
Typ
±10
±20
±2
±2
±2
±2
±1
70
–
–
–
–
–
–
–
–
–
250
250
250
-1
j
=+35°C
Max
±0.9
±30
±30
5.2
±1
±2
±2
±2
80
60
32
21
–
–
–
–
–
–
–
–
250
250
250
-1L
LSB/°C
Units
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
MHz
MHz
Bits
dB
%
%
%
%
%
Units
MHz
MHz
MHz
21