XC6VSX475T-2FFG1759E Xilinx Inc, XC6VSX475T-2FFG1759E Datasheet - Page 40

• Manufacturer Part Number: XC6VSX475T-2FFG1759E
• Description: IC FPGA VIRTEX 1759FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™ 6 SXTr

Specifications of XC6VSX475T-2FFG1759E

• Number Of Logic Elements/cells: 476160
• Number Of Labs/clbs: 37200
• Total Ram Bits: 39223296
• Number Of I /o: 840
• Number Of Gates: -
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1759-BBGA, FCBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: XC6VSX475T-2FFG1759I; XC6VSX475T-2FFG1759I

Block RAM and FIFO Switching Characteristics
Table 56: Block RAM and FIFO Switching Characteristics
DS152 (v3.2) April 1, 2011
Product Specification
Block RAM and FIFO Clock-to-Out Delays
T
T
T
T
T
T
T
T
T
T
T
T
Setup and Hold Times Before/After Clock CLK
T
T
T
T
T
T
T
T
RCKO_DO
RCKO_DO_ECC
RCKO_DO_ECC_REG
RCKO_CASC
RCKO_CASC_REG
RCKO_FLAGS
RCKO_POINTERS
RCKO_SDBIT_ECC
RCKO_SDBIT_ECC_REG
RCKO_PARITY_ECC
RCKO_RDADDR_ECC
RCKO_RDADDR_ECC_REG
RCCK_ADDR
RDCK_DI
RDCK_DI_ECC
RCCK_CLK
RCCK_RDEN
RCCK_REGCE
RCCK_RSTREG
RCCK_RSTRAM
/T
and T
/T
RCKD_DI
Symbol
/T
/T
RCKC_CLK
and
/T
/T
RCKC_ADDR
RCKC_RDEN
/T
/T
and
RCKC_REGCE
RCKD_DI_ECC
RCKO_DO_REG
RCKC_RSTREG
RCKC_RSTRAM
and
and
(1)
Clock CLK to DOUT output (without output
register)
Clock CLK to DOUT output (with output
register)
Clock CLK to DOUT output with ECC
(without output register)
Clock CLK to DOUT output with ECC (with
output register)
Clock CLK to DOUT output with Cascade
(without output register)
Clock CLK to DOUT output with Cascade
(with output register)
Clock CLK to FIFO flags outputs
Clock CLK to FIFO pointers outputs
Clock CLK to BITERR (with output
register)
Clock CLK to BITERR (without output
register)
Clock CLK to ECCPARITY in ECC encode
only mode
Clock CLK to RDADDR output with ECC
(without output register)
Clock CLK to RDADDR output with ECC
(with output register)
ADDR inputs
DIN inputs
DIN inputs with block RAM ECC in
standard mode
DIN inputs with block RAM ECC encode
only
DIN inputs with FIFO ECC in standard
mode
Inject single/double bit error in ECC mode
Block RAM Enable (EN) input
CE input of output register
Synchronous RSTREG input
Synchronous RSTRAM input
(9)
(9)
(2)(3)
(4)(5)
(9)
(8)
Description
(9)
(4)(5)
(4)
(2)(3)
(2)
www.xilinx.com
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
(6)
(7)
0.47/
0.84/
0.47/
0.68/
0.77/
0.90/
0.31/
0.18/
0.22/
0.32/
1.60
0.60
2.62
0.71
2.49
1.29
0.74
0.90
0.62
2.21
0.86
0.73
0.76
0.27
0.30
0.30
0.30
0.30
0.27
0.26
0.25
0.23
0.23
-3
0.53/
0.95/
0.52/
0.75/
0.87/
1.02/
0.35/
0.19/
0.24/
0.36/
1.79
0.66
2.89
0.77
2.77
1.41
0.81
0.98
0.68
2.46
0.94
0.79
0.82
0.29
0.32
0.32
0.32
0.32
0.28
0.27
0.27
0.24
0.24
Speed Grade
-2
0.62/
1.11/
0.59/
0.85/
1.02/
1.20/
0.41/
0.22/
0.28/
0.41/
2.08
0.75
3.30
0.86
3.18
1.58
0.91
1.09
0.76
2.84
1.06
0.90
0.92
0.32
0.34
0.34
0.34
0.34
0.29
0.30
0.31
0.26
0.27
-1
0.66/
1.26/
0.68/
0.97/
1.16/
1.56/
0.44/
0.24/
0.31/
0.46/
2.36
0.83
3.73
0.94
3.61
1.79
0.98
1.21
0.82
3.23
1.18
1.00
1.02
0.34
0.36
0.36
0.36
0.36
0.29
0.31
0.33
0.27
0.29
-1L
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
40