XC2VP40-6FF1152C Xilinx Inc, XC2VP40-6FF1152C Datasheet - Page 90

• Manufacturer Part Number: XC2VP40-6FF1152C
• Description: FPGA Virtex-II Pro Family 43632 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 1152-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-II Pror

Specifications of XC2VP40-6FF1152C

• Package: 1152FCBGA
• Family Name: Virtex-II Pro
• Device Logic Units: 43632
• Number Of Registers: 38784
• Maximum Internal Frequency: 1200 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 692
• Ram Bits: 3538944
• Number Of Logic Elements/cells: 43632
• Number Of Labs/clbs: 4848
• Total Ram Bits: 3538944
• Number Of I /o: 692
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5392905

Table 28: RocketIO X Fabric Interface Characteristics
Table 29: RocketIO RXUSRCLK Switching Characteristics
Table 30: RocketIO RXUSRCLK2 Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
TX/RXUSRCLK frequency
TX/RXUSRCLK2 frequency
Setup and Hold Relative to Clock
(RXUSRCLK)
Clock to Out
Clock
Setup and Hold Relative to Clock
(RXUSRCLK2)
Clock to Out
CHBONDI control inputs
CHBONDO control outputs
RXUSRCLK minimum pulse width, High
RXUSRCLK minimum pulse width, Low
RXRESET control input
RXPOLARITY control input
ENCHANSYNC control input
RXNOTINTABLE status outputs
RXDISPERR status outputs
RXCHARISCOMMA status outputs
RXREALIGN status output
RXCOMMADET status output
RXLOSSOFSYNC status outputs
RXCLKCORCNT status outputs
RXBUFSTATUS status outputs
RXCHECKINGCRC status output
RXCRCERR status output
CHBONDDONE status output
RXCHARISK status outputs
RXRUNDISP status outputs
RXDATA data outputs
R
Description
Description
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
T
T
T
T
GCCK
GCCK
GCCK
GCCK
T
T
www.xilinx.com
T
T
T
T
T
T
T
T
GCKST
_RRST/T
_RPOL/T
_ECSY/T
T
T
T
T
GCKST
T
GCKST
GCKST
GCKST
_CHBI/T
GCKST
GCKCO
GCKST
GCKST
GCKST
GCKST
GCKST
GCKST
GCKDO
F
T
GCKST
F
T
TXRXUCLK2
Symbol
Symbol
Symbol
GPWH
TXRXUCLK
GPWL
_RCCCNT
_RCMCH
_RDERR
_RCCRC
_RCRCE
_RBSTA
_ALIGN
_RRDIS
_CMDT
_RLOS
_CHBD
_RKCH
_CHBO
_RNIT
_RDAT
_RX
_RX
GCKC
GCKC
GCKC
GCKC
_RRST
_RPOL
_ECSY
_CHBI
0.00/ 0.12
0.02/ 0.00
0.02/ 0.00
0.02/ 0.00
125.00
62.50
0.50
0.45
0.50
0.50
0.50
2.83
2.83
0.50
0.50
0.50
0.41
0.41
0.50
0.41
0.36
0.36
0.50
Min
-7
-7
All Speed Grades
Speed Grade
Speed Grade
0.00/ 0.12
0.02/ 0.00
0.02/ 0.00
0.02/ 0.00
0.50
2.83
2.83
0.50
0.50
0.50
0.41
0.41
0.50
0.41
0.45
0.40
0.40
0.50
0.50
0.50
0.50
Typ
-6
-6
0.00/ 0.14
0.02/ 0.00
0.02/ 0.00
0.02/ 0.00
212.50
250.00
Max
0.55
4.50
4.50
0.55
0.55
0.55
0.46
0.46
0.55
0.46
0.50
0.44
0.44
0.55
0.55
0.55
0.55
-5
-5
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
Units
MHz
MHz
19