XC2VP40-6FF1152C Xilinx Inc, XC2VP40-6FF1152C Datasheet - Page 86

no-image

XC2VP40-6FF1152C

Manufacturer Part Number
XC2VP40-6FF1152C
Description
FPGA Virtex-II Pro Family 43632 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 1152-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP40-6FF1152C

Package
1152FCBGA
Family Name
Virtex-II Pro
Device Logic Units
43632
Number Of Registers
38784
Maximum Internal Frequency
1200 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
692
Ram Bits
3538944
Number Of Logic Elements/cells
43632
Number Of Labs/clbs
4848
Total Ram Bits
3538944
Number Of I /o
692
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q5392905

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2VP40-6FF1152C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC2VP40-6FF1152C
Manufacturer:
XILINX
0
Part Number:
XC2VP40-6FF1152C
Manufacturer:
XILINX
Quantity:
80
Part Number:
XC2VP40-6FF1152C
0
Part Number:
XC2VP40-6FF1152CGB
Manufacturer:
XILINX
0
Table 24: RocketIO X Receiver Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. The XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
2.
3.
4.
Receive total jitter tolerance
using default equalization and PRBS-15
pattern
Receive random jitter tolerance
Receive sinusoidal jitter tolerance
measured at 70 MHz
Receive deterministic jitter tolerance
Receive latency
RXUSRCLK duty cycle
RXUSRCLK2 duty cycle
Differential receive input sensitivity
UI = Unit Interval
Receive latency delay RXP/RXN to RXDATA. Refer to
This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled. If these functions are both
disabled, the maximum will be near the typical values.
R
Description
(3)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Symbol
T
T
T
T
T
T
T
V
RX2DC
RJTOL
SJTOL
DJTOL
RXLAT
RXDC
JTOL
EYE
RocketIO X Transceiver User Guide
www.xilinx.com
Conditions
2.488 Gb/s
3.125 Gb/s
2.488 Gb/s
3.125 Gb/s
2.488 Gb/s
3.125 Gb/s
2.488 Gb/s
3.125 Gb/s
4.25 Gb/s
6.25 Gb/s
4.25 Gb/s
6.25 Gb/s
4.25 Gb/s
6.25 Gb/s
4.25 Gb/s
6.25 Gb/s
(1)
Min
45
45
for more information on calculating latency.
0.80
0.80
0.80
0.80
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.55
0.55
0.55
0.50
Typ
120
25
50
50
Max
0.65
0.65
0.65
0.65
0.15
0.15
0.15
0.15
0.45
0.45
0.45
0.45
250
34
55
55
(4)
RXUSRCLK cycles
Units
Module 3 of 4
mV
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
%
%
(2)
15

Related parts for XC2VP40-6FF1152C