XC2VP40-6FF1152C Xilinx Inc, XC2VP40-6FF1152C Datasheet - Page 45

• Manufacturer Part Number: XC2VP40-6FF1152C
• Description: FPGA Virtex-II Pro Family 43632 Cells 1200MHz 0.13um/90nm (CMOS) Technology 1.5V 1152-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-II Pror

Specifications of XC2VP40-6FF1152C

• Package: 1152FCBGA
• Family Name: Virtex-II Pro
• Device Logic Units: 43632
• Number Of Registers: 38784
• Maximum Internal Frequency: 1200 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 692
• Ram Bits: 3538944
• Number Of Logic Elements/cells: 43632
• Number Of Labs/clbs: 4848
• Total Ram Bits: 3538944
• Number Of I /o: 692
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5392905

Figure 30
LVDS_25_DCI and LVDSEXT_25_DCI I/O standards. For a
complete list, see the
Guide
On-Chip Differential Termination
Virtex-II Pro provides a true 100Ω differential termination
(DT) across the input differential receiver terminals. The
LVDS_25_DT,
ULVDS_25_DT standards support on-chip differential termi-
nation.
DS083 (v4.7) November 5, 2007
Product Specification
Recommended
Z 0
Conventional
Conventional
Transmit
DCI Receive
Reference
Resistor
.
Figure 30: LVDS DCI Usage Examples
provides examples illustrating the use of the
R
NOTE: Only LVDS25_DCI is supported (V
LVDS_25_DCI and LVDSEXT_25_DCI Receiver
LVDSEXT_25_DT,
Virtex-II Pro Platform FPGA User
VRN = VRP = R = Z 0
Z 0
Z 0
Z 0
Z 0
50 Ω
V
V
CCO
LDT_25_DT,
CCO
CCO
2R
2R
2R
2R
= 2.5V only)
2R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Virtex-II Pro
LVDS DCI
DS083-2_65c_022103
Virtex-II Pro
LVDS
www.xilinx.com
and
The on-chip input differential termination in Virtex-II Pro
provides major advantages over the external resistor or the
DCI termination solution:
•
•
•
•
Figure 31
LVDS_25_DT,
ULVDS_25_DT I/O standards. For further details, refer to
Solution Record 17244
FPGA User Guide
Recommended
Z 0
Conventional
Conventional
Transmit,
On-Chip
Differential
Termination
Receive
Eliminates the stub at the receiver completely and
therefore greatly improve signal integrity
Consumes less power than DCI termination
Supports LDT (not supported by DCI termination)
Frees up VRP/VRN pins
Figure 31: LVDS Differential Termination Usage
provides examples illustrating the use of the
NOTE: Only 2.5V LVDS standards are supported (V
LVDSEXT_25_DT,
LDT_25_DT, and ULVDS_25_DT Receiver
for more design information.
LVDS_25_DT, LVDSEXT_25_DT,
. Also see the
Examples
Z 0
Z 0
Z 0
Z 0
50 Ω
Virtex-II Pro Platform
100Ω
LDT_25_DT,
2R
Virtex-II Pro
LVDS On-Chip
Differential
Termination
CCO
DS083-2_65e_052703
Module 2 of 4
Virtex-II Pro
LVDS
= 2.5V only)
and
34