IDT74SSTV16859PA IDT, Integrated Device Technology Inc, IDT74SSTV16859PA Datasheet - Page 3
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IDT74SSTV16859PA
Manufacturer Part Number
IDT74SSTV16859PA
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT74SSTV16859PA.pdf
(6 pages)
Specifications of IDT74SSTV16859PA
Logic Family
SSTV
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
13
Number Of Inputs
13
Number Of Outputs
26
High Level Output Current
-20mA
Low Level Output Current
20mA
Package Type
TSSOP
Propagation Delay Time
2.8ns
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
200(Min)MHz
Mounting
Surface Mount
Pin Count
64
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Not Compliant
PIN DESCRIPTION
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
NOTE:
1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature.
IDT74SSTV16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
Center PAD
Symbol
Pin Names
Q
D
RESET
V
I
r
V
V
I
DDD
r
r
O(Δ)
C
GND
DD
OH
1
V
V
OL
CLK
1
OH
I
CLK
OL
V
IK
I
DDQ
REF
I
- Q
- D
DD
13
13
Parameter
Control Inputs
All Inputs
Static Standby
Static Operating
Dynamic Operating (Clock Only)
Dynamic Operating
(Per Each Data Input)
Output HIGH
Output LOW
| r
Data Inputs
CLK and CLK
RESET
OH
- r
OL
| each separate bit
A
= –40°C to +85°C, V
Description
Data Output
Ground
Output-stage drain power voltage
Logic power voltage
Asynchronous reset input - resets registers and disables data and clock differential input recievers
Input reference voltage
Positive master clock input
Negative master clock input
Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of CLK
Ground (MLF package only)
(1)
DD
= 2.5V ±0.2V, V
Test Conditions
V
V
V
V
V
V
I
I
I
CLK and CLK Switching 50% Duty Cycle.
I
CLK and CLK Switching 50% Duty Cycle. One Data Input
Switching at Half Clock Frequency, 50% Duty Cycle.
V
V
V
V
V
V
O
O
O
O
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
ICR
I
= 0, V
= 0, V
= 0, V
= 0, V
= V
= 2.3V to 2.7V, I
= 2.3V to 2.7V, I
= 2.3V, I
= 2.3V, I
= 2.3V to 2.7V, I
= 2.3V, I
= 2.7V,VI = V
= 2.3V to 2.7V, I
= 2.5V, T
= 2.5V, V
= 1.25V, V
DD
DD
DD
DD
DD
or GND
= 2.7V, RESET = V
= 2.7V, RESET = V
= 2.7V, RESET = V
= 2.7V, RESET = GND
OH
I
OL
= −18mA
A
I
= V
= 25°C, I
I (PP)
= 16mA
= -16mA
DDQ
DD
REF
OH
OL
OH
OH
= 360mV
or GND
= 2.5V ±0.2V
± 310mV
= 100μA
= -100μA
= -20mA
= 20mA
OH
= -20mA
3
DD
DD
DD
, V
, V
, V
I
I
I
= V
= V
= V
IH (AC)
IH (AC)
IH (AC)
or V
or V
or V
IL (AC)
IL (AC)
IL (AC)
,
,
V
INDUSTRIAL TEMPERATURE RANGE
DD
Min.
1.95
—
—
—
—
—
—
—
—
—
7
7
2
2
2
– 0.2
Typ.
—
—
—
—
—
—
—
—
43
—
—
—
—
—
—
6
Max.
–1.2
0.35
0.01
0.2
±5
—
—
20
—
—
20
20
4
3
3
3
MHz/Data
μA/Clock
μA/Clock
MHz
Input
Unit
mA
μA
pF
Ω
Ω
Ω
V
V
V