IDT74SSTV16859PA IDT, Integrated Device Technology Inc, IDT74SSTV16859PA Datasheet

IDT74SSTV16859PA

Manufacturer Part Number

IDT74SSTV16859PA

Description

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT74SSTV16859PA.pdf (6 pages)

Specifications of IDT74SSTV16859PA

Logic Family

SSTV

Logical Function

Registered Buffer

Number Of Elements

Number Of Bits

Number Of Inputs

Number Of Outputs

High Level Output Current

-20mA

Low Level Output Current

20mA

Package Type

TSSOP

Propagation Delay Time

2.8ns

Operating Supply Voltage (typ)

2.5V

Operating Supply Voltage (max)

2.7V

Operating Supply Voltage (min)

2.3V

Clock-edge Trigger Type

Posit/Negat-Edge

Polarity

Non-Inverting

Technology

CMOS

Frequency (max)

200(Min)MHz

Mounting

Surface Mount

Pin Count

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Lead Free Status / RoHS Status

Not Compliant

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FEATURES:

• 2.3V to 2.7V Operation

• SSTL_2 Class II style data inputs/outputs

• Differential CLK input

• RESET control compatible with LVCMOS levels

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

• Available in 56 pin VFQFPN and 64 pin TSSOP packages

INDUSTRIAL TEMPERATURE RANGE

APPLICATIONS:

• Ideally suited for DIMM DDR registered applications

FUNCTIONAL BLOCK DIAGRAM

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

IDT74SSTV16859

13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O

machine model (C = 200pF, R = 0)

2008 Integrated Device Technology, Inc.

RESET

CLK

REF

13-BIT TO 26-BIT REGISTERED

BUFFER WITH SSTL I/O

TO 12 OTHER CHANNELS

DESCRIPTION:

2.7V V

are SSTL_2 level compatible with JEDEC standard for SSTL_2.

power-up phase. RESET, which can be operated independent of CLK and

CLK, must be held in the low state during power-up in order to ensure

predictable outputs (low state) before a stable clock has been applied.

registers, and force all outputs to a low state, before a stable clock has been

applied. With inputs held low and a stable clock applied, outputs will remain

low during the Low-to-High transition of RESET.

The SSTV16859 is a 13-bit to 26-bit registered buffer designed for 2.3V-

RESET is an LVCMOS input since it must operate predictably during the

RESET, when in the low state, will disable all input receivers, reset all

and supports low standby operation. All data inputs and outputs

INDUSTRIAL TEMPERATURE RANGE

IDT74SSTV16859

NOVEMBER 2008

DSC-5947/9

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IDT74SSTV16859PA Summary of contents

Page 1

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: • 2.3V to 2.7V Operation • SSTL_2 Class II style data inputs/outputs • Differential CLK input • RESET control compatible with LVCMOS levels • Latch-up performance exceeds 100mA • ESD ...

Page 2

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O PIN CONFIGURATIONS GND Q 13B V DDQ Q 12B Q 11B Q 10B ...

Page 3

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O PIN DESCRIPTION Pin Names Description Data Output 1 13 GND Ground V Output-stage drain power voltage DDQ V Logic power voltage DD RESET Asynchronous reset input - resets ...

Page 4

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O OPERATING CHARACTERISTICS, T Symbol Parameter V Supply Voltage DD V Output Supply Voltage DDQ V Reference Voltage ( REF REF DDQ V Termination Voltage TT V Input Voltage I ...

Page 5

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O TEST CIRCUITS AND WAVEFORMS (V LVCMOS RESET Input t INACT I 10% DD (see note 2) Voltage and Current Waveforms Inputs Active and Inactive Times t W Input ...

Page 6

IDT74SSTV16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O ORDERING INFORMATION XX XX SSTV Temp. Range Family Device Type Package PA NL 859 16 74 CORPORATE HEADQUARTERS San Jose, CA 95138 6 INDUSTRIAL TEMPERATURE RANGE Thin Shrink ...

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