IDT82V3001APV IDT, Integrated Device Technology Inc, IDT82V3001APV Datasheet - Page 14

• Manufacturer Part Number: IDT82V3001APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3001APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.5
a Limiter, a Loop Filter, a Digital Control Oscillator and Dividers.
3.5.1
signal from the TIE Control Circuit with the feedback signal from the
Frequency Select Circuit, and outputs an error signal corresponding to
the phase difference between the two. This error signal is then sent to
the Limiter circuit for phase slope control.
selected by F_sel1 and F_sel0 pins. Refer to
Phase Detector and the Limiter are not active and the input reference
signal is not used.
3.5.2
transient conditions with a maximum output phase slope of 5 ns per 125
µs. This well meets AT&T TR62411 and Telcordia GR-1244-CORE
specifications, which specify the maximum phase slope of 7.6 ns per
125 µs and 81 ns per 1.326 ms respectively.
FUNCTIONAL DESCRIPTION
IDT82V3001A
As shown in
In Normal Mode, the Phase Detector compares the virtual reference
The feedback signal can be 8 kHz, 2.048 MHz or 1.544 MHz, as
In Freerun or Holdover Mode, the Frequency Select Circuit, the
The Limiter is used to ensure that the DPLL responds to all input
DPLL BLOCK
PHASE DETECTOR (PHD)
LIMITER
Figure -
Loop Filter
Fraction_C6
Fraction_T1
8, the DPLL Block consists of a Phase Detector,
Limiter
FLOCK
Table - 3
for details.
Figure - 8 DPLL Block Diagram
Detector
Phase
25.248 MHz
32.768 MHz
24.704 MHz
Virtual Reference
14
Feedback
Signal
Detector, limits the phase slope within 5 ns per 125 µs and sends the
limited signal to the Loop Filter.
FLOCK pin to high, the device will enter fast lock mode. In this mode,
the Limiter is disabled and the DPLL will lock to the incoming reference
within 500 ms.
3.5.3
and AT&T TR62411 requirements. This Loop Filter works similarly to a
first order low pass filter with 2.1 Hz cutoff frequency for the three valid
input reference signals (8 kHz, 2.048 MHz or 1.544 MHz).
directly or via the Fraction blocks, in which E1, T1 and C6 signals are
generated.
In Normal Mode, the Limiter receives the error signal from the Phase
The fast lock mode is a submode of Normal Mode. By setting the
The Loop Filter ensures that the jitter transfer meets ETS 300 011
The output of the Loop Filter goes to the Digital Control Oscillator
Output Interface
E1_Divider
C6_Divider
T1_Divider
F_sel1 F_sel0
Frequency
Selection
LOOP FILTER
Circuit
WAN PLL WITH SINGLE REFERENCE INPUT
C1.5o
C3o
C2o
C4o
C8o
C16o
C32o
F8o
F16o
F32o
RSP
TSP
C6o
F0o
October 15, 2008