IDT82V3001APV IDT, Integrated Device Technology Inc, IDT82V3001APV Datasheet - Page 13

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IDT82V3001APV

Manufacturer Part Number
IDT82V3001APV
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82V3001APV

Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
SSOP
Pin Count
56
Mounting
Surface Mount
Lead Free Status / RoHS Status
Not Compliant

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applying a logic low pulse to the TCLR pin. The reset pulse should be at
least 300 ns.
time periods and then turns back to Normal Mode, the TIE Control
Circuit should not be enabled. This will prevent undesired accumulated
FUNCTIONAL DESCRIPTION
IDT82V3001A
The phase difference in the Storage Circuit can be cleared by
When the IDT82V3001A primarily enters Holdover Mode for short
Previous Fref
Current Fref
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Previous Fref
Current Fref
Time = 0.00 s
Time = 0.25 s
Time = 0.50 s
Time = 0.75 s
Time = 1.0 s
Time = 1.25 s
Time = 1.50 s
Time = 1.75 s
Figure - 7 State Switch with TIE Control Block Disabled
Figure - 6 State Switch with TIE Control Block Enabled
13
phase change between the input and output.
state switching, the phase of the output signal will align with that of the
new reference. The phase slope limited to 5 ns per 125 µs.
shows the phase transient resulting from a state switch with the TIE
Control Block disabled.
If the TIE Control Block is disabled manually or automatically during
WAN PLL WITH SINGLE REFERENCE INPUT
Output Clock
Output Clock
Input Clock
Input Clock
October 15, 2008
Figure - 7

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