MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 90

• Manufacturer Part Number: MCIMX255AJM4A
• Manufacturer: Freescale

Specifications of MCIMX255AJM4A

• Lead Free Status / RoHS Status: Compliant

3.7.11
The I
Figure 64
parameters (IC1–IC6) shown in the figure.
1
90
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
I2CLK
IC10
IC11
IC12
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
•
•
•
•
•
•
•
I2DAT
ID
2
C communication protocol consists of the following seven elements:
Start
Data source/recipient
Data direction
Slave acknowledge
Data
Data acknowledge
Stop
shows the timing of the I
I2CLK cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2CLK Clock
LOW Period of the I2CLK Clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
Capacitive load for each bus line (C
Inter IC Communication (I
IC2
START
i.MX25 Applications Processor for Automotive Products, Rev. 4
IC10
Table 67. I2C Module Timing Parameters: 3.0 V +/–0.30 V
IC6
IC8
IC1
Parameter
IC10
Figure 64. I
2
IC5
C module.
IC4
b
)
2
C Module Timing Diagram
IC11
Table 67
2
C) Timing
IC11
and
IC7
Table 68
START
Standard Mode
Min.
250
4.0
4.0
4.0
4.7
4.7
4.7
10
0
-
-
-
1
describe the I
3.45
Max.
1000
300
400
-
-
-
-
-
-
-
-
2
IC3
20+0.1C
20+0.1C
STOP
100
Min.
2.5
0.6
0.6
0.6
1.3
0.6
1.3
0
2
Fast Mode
-
Freescale Semiconductor
1
C module timing
3
b
b
4
4
IC9
Max.
0.9
300
300
400
-
-
-
-
-
-
-
START
2
Unit
pF
ns
ns
ns
s
s
s
s
s
s
s
s