MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 105
MCIMX255AJM4A
Manufacturer Part Number
MCIMX255AJM4A
Description
Manufacturer
Freescale
Datasheet
1.MCIMX255AJM4A.pdf
(132 pages)
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3.7.17.2
Figure 79
parameters (SS1–SS51) shown in the figure.
Freescale Semiconductor
SS11
SS13
SS20
SS21
SS47
SS1
SS2
SS3
SS4
SS5
SS7
SS9
ID
shows the timing for the SSI receiver with internal clock.
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
Oversampling clock period
AUDn_TXFS (wl)
SSI Receiver Timing with Internal Clock
AUDn_TXFS (bl)
AUDn_RXD
AUDn_RXC
AUDn_TXC
(Output)
(Output)
(Output)
(Output)
(Input)
i.MX25 Applications Processor for Automotive Products, Rev. 4
Figure 79. SSI Receiver Internal Clock Timing Diagram
SS48
SS2
Table 80. SSI Receiver Timing with Internal Clock
SS7
Parameter
Oversampling Clock Operation
SS47
Internal Clock Operation
SS1
SS11
SS9
SS20
SS51
SS5
SS4
SS50
SS21
Table 80
15.04
Min.
81.4
36.0
36.0
10.0
0.0
—
—
—
—
—
—
SS49
SS3
describes the timing
Max.
15.0
15.0
15.0
15.0
6.0
6.0
—
—
—
—
—
—
SS13
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
105
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