MCIMX255AJM4A Freescale, MCIMX255AJM4A Datasheet - Page 60
MCIMX255AJM4A
Manufacturer Part Number
MCIMX255AJM4A
Description
Manufacturer
Freescale
Datasheet
1.MCIMX255AJM4A.pdf
(132 pages)
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3.7.6.1.2
The following diagrams and tables specify the timings related to the SDRAMC module which interfaces
with the mobile DDR SDRAM.
1
60
SD17
SD18
SD19
SD20
Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.
ID
SD16
ID
DQ and DQM setup time to DQS
DQ and DQM hold time to DQS
Write cycle DQS falling edge to SDCLK output delay time
Write cycle DQS falling edge to SDCLK output hold time
DQM (output)
DQS (output)
DQ (output)
SDCLK
SDCLK
CKE output delay time
Mobile DDR SDRAM–Specific Parameters
Table 46. Mobile DDR SDRAM Write Cycle Timing Parameters
Figure 29. Mobile DDR SDRAM Write Cycle Timing Diagram
i.MX25 Applications Processor for Automotive Products, Rev. 4
Table 45. SDRAM Self-Refresh Cycle Timing Parameters
Parameter
SD17
SD17
Parameter
Data
DM
SD18
SD18
Data
DM
Data
DM
SD17
SD17
Symbol
tCKS
Data
DM
SD18
SD18
Data
DM
Min.
1.8
Symbol
Data
DM
tDSS
tDSH
tDS
tDH
SD19
1
Freescale Semiconductor
Data
DM
Min.
0.95
0.95
SD20
Max.
1.8
1.8
—
Data
DM
Max.
—
—
—
—
Unit
ns
Unit
ns
ns
ns
ns
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