MCIMX253CJM4A Freescale, MCIMX253CJM4A Datasheet - Page 98
MCIMX253CJM4A
Manufacturer Part Number
MCIMX253CJM4A
Description
Manufacturer
Freescale
Datasheet
1.MCIMX253CJM4A.pdf
(142 pages)
Specifications of MCIMX253CJM4A
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SIMx_DATAy_RX_TX
3.7.14.1
SIM cards may have internal reset, or active low reset. The following subset describes the reset sequences
in these two cases.
3.7.14.1.1
Figure 69
following steps:
Table 73
3.7.14.1.2
Figure 70
following steps:
98
SIMn_SVENm
SIMx_CLKy
•
•
•
•
•
•
•
•
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.
The card must send a response on SIMx_DATAy_RX_TX acknowledging the reset between
400–40000 clock cycles after T0.
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.
SIMx_RSTy must remain low for at least 40,000 clock cycles after T0 (no response is to be
received on RX during those 40,000 clock cycles)
SIMx_RSTy is asserted (at time T1)
SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be
received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1.
defines the general timing requirements for the SIM interface.
shows the reset sequence for SIM cards with active low reset. The reset sequence comprises the
shows the reset sequence for SIM cards with internal reset. The reset sequence comprises the
Ref No.
SIM Reset Sequences
1
2
SIM Cards with Internal Reset
SIM Cards with Active Low Reset
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
T0
Table 73. Timing Specifications, Internal Reset Card Reset Sequence
1
Figure 69. Internal Reset Card Reset Sequence
2
Min.
400
—
RESPONSE
40,000
Max.
200
Freescale Semiconductor
clk cycles
clk cycles
Units
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