MCIMX253CJM4A Freescale, MCIMX253CJM4A Datasheet
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MCIMX253CJM4A
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... At the core of the i.MX25 is Freescale's fast, proven, power-efficient implementation of the ARM926EJ-S core, with speeds 400 MHz. The i.MX25 includes support for up to 133-MHz DDR2 memory, integrated 10/100 Ethernet MAC, and two on-chip USB PHYs ...
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... On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY. • Fast Ethernet—For rapid external communication, a Fast Ethernet Controller (FEC) is included. • i.MX25 only supports Little Endian mode. i.MX25 Applications Processor for Consumer and Industrial Products, Rev Freescale Semiconductor ...
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... MCIMX258CJM4 i.MX253 MCIMX253DJM4A i.MX257 MCIMX257DJM4A i.MX257 MCIMX257DJM4AR2 i.MX253 MCIMX253CJM4A i.MX257 MCIMX257CJM4A i.MX258 MCIMX258CJM4A i.MX257 MCIMX257CJN4A 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: Indicated by the Icon (!) i ...
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... Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes MCIMX258 ARM926EJ-S™ 400 MHz 16K I/D 128 KB Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Freescale Semiconductor ...
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... Shared Domain SDMA Peripherals UART(3) CSPI(2) ADC/TSC Audio/Power Management Figure 1. i.MX25 Simplified Interface Block Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Ext. Graphics NAND Camera LCD Display 1 Accelerator Flash Sensor ARM ® Processor Domain (AP) LCDC / CSI ...
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... M3IF provides arbitration between multiple masters requesting access to the external memory. • Enhanced SDRAM/LPDDR memory controller (ESDCTL) interfaces to DDR2 and SDR interfaces. • NAND Flash controller (NFC) provides an interface to NAND Flash memories. • Wireless External Interface Memory controller (WEIM) interfaces to NOR Flash and PSRAM. Brief Description Freescale Semiconductor ...
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... Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Brief Description Each Enhanced Periodic Interrupt Timer (EPIT 32-bit set-and-forget timer that starts counting after the EPIT is enabled by software capable of providing precise interrupts at regular intervals with minimal processor intervention ...
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... The SIM is designed to facilitate communication to SIM cards or pre-paid phone cards. The System JTAG Controller (SJC) provides debug and test control with maximum security. The SLCDC module transfers data from the display memory buffer to the external display device. peripheral ownership and access rights to an owned peripheral. Freescale Semiconductor ...
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... Used to select the ARM clock source from MPLL out or from external EXT_ARMCLK. In normal operation, CLK_SEL should be connected to GND. EXT_ARMCLK Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin must be externally connected to GND or VDD. Aside from factory use, this pin can also be configured (through muxing) to work as a normal GPIO. ...
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... GND. UPLL_BYPCLK Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin must be externally connected to GND or VDD. Aside from factory use, this pin can also be configured (through muxing) to work as a normal GPIO. ...
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... Core supply voltage (at 266 MHz) Core supply voltage (at 400 MHz) 1 Coin battery BAT_VDD I/O supply voltage, GPIO NFC,CSI,SDIO i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor CAUTION Table 5 may cause permanent Table 5. DC Absolute Maximum Ratings Symbol QV DD ...
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... DD_OSC24M V 1.4 — DD_PLL V 3.0 3.3 DD_tsc Vref 2 DD_tsc FUSEV 3.3 ± 5% — DD (program mode) V 1.0 — DD_ T –40 — A can be connected to DD_BAT Table 7 Freescale Semiconductor Max. Units 3.6 — 1.95 V 1.9 V 3.6 V 3.43 V 3.6 V 3.6 V 1. DD_tsc 3 ...
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... Parameter Analog supply USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD, USBPHY1_VDDA (3.3 V) Analog supply USBPHY2_VDD (3.3 V) All supplies 1 Values must be verified i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Symbol I program I ). program Table 8. Interface Frequency Limits Table 9. USB PHY Current Consumption Conditions Full speed ...
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... Applications Processor for Consumer and Industrial Products, Rev Table 10. i.MX25 Power Mode Settings Power Mode Wait Stop/Sleep Off On Off On On Off 1 Run (266 MHz) Run (400 MHz) — Active @ Active @ 266 MHz 400 MHz On Off Off Off On On Off On On Off Off On On Freescale Semiconductor ...
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... Table 12. iMX25 Reduced Power Mode Current Consumption Power Group Power Supply BAT_VDD BAT_VDD i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Current Consumption for Power Modes Voltage Setting Doze Wait 3 ...
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... Other power-up sequences may be possible; however, the above sequence has been verified and is recommended. • There is a 1-ms minimum time between supplies coming up, and a 1-ms minimum time between POR_B assert and deassert. i.MX25 Applications Processor for Consumer and Industrial Products, Rev CAUTION NOTE NOTE Freescale Semiconductor ...
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... OSC24M_VDD, MPPLL_VDD, UPLL_VDD and FUSEVDD no less than 1ms and no greater than 32 ms after QVDD reaches 90% of 1.2V. FUSEVDD is tied to GND if fuses are not being programmed. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Figure 2. Power-Up Sequence Diagram NOTE 17 ...
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... Common supplies are bundled according to the i.MX25 power-up sequence requirements. Peak numbers are provided for system designers so that the i.MX25 power supply requirements are satisfied during startup and transient conditions. Freescale recommends that system current measurements are taken with customer-specific use-cases to reflect the normal operating conditions in the end system ...
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... Refer to The values mentioned above should not be taken as a typical max run data for specific use cases. These values are Absolute MAX data. Freescale recommends that the system current measurements are taken with customer-specific use-cases to reflect normal operating conditions in the end system 3 ...
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... External Signals and Pin Multiplexing chapter of the i.MX25 Reference Manual for details). i.MX25 Applications Processor for Consumer and Industrial Products, Rev Condition Single layer board (1s) Four layer board (2s2p) — — Natural convection NOTE Symbol Value Unit R 46 °C/W eJMA R 29 °C/W eJMA R 22 °C/W eJB R 13 °C/W eJCtop 2 °C/W JT Freescale Semiconductor ...
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... Minimum condition: BCS model, 1.95 V, and –40 °C. Typical condition: typical model, 1.8 V, and 25 °C. Maximum condition: wcs model, 1.65 V, and 105 °C. 3. Typical condition: typical model, 1.8 V, and 25 °C. Maximum condition: BCS model, 1.95 V, and 105 °C. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Symbol Test Conditions Min. ...
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... V — — 150 nA 80 — — 1180 nA — — 1220 nA Typ. Max. Units — — V — 0.28 V — — mA — — mA — OVDD + 0.3 V — OVDD/2 – 0.125 V Freescale Semiconductor Notes 1 1 — — — Notes — — — ...
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... Table 18. GPIO DC Electrical Characteristics DC Electrical Characteristics High-level output voltage Low-level output voltage High-level output current for slow mode High-level output current for fast mode i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Test Min. Conditions — –0.3 — 0.25 Vtt — ...
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... OVDD –0.3 V — 0.3 OVDD 370 — 420 mV 290 320 OVDD — — — — 0.5 OVDD 18 100 120 K 85 100 120 K — — 100 117 — 184 0.0001 0.0001 64 104 0.0001 0.0001 Freescale Semiconductor — — V — V — ...
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... AC Electrical Characteristics This section provides the AC parameters for slow and fast I/O. Figure 3 shows the load circuit for output. propagation waveforms. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Symbol Test Conditions IIN OVDD = 3 OVDD = 3 OVDD = 1 OVDD = 1 ...
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... Output (at pad) i.MX25 Applications Processor for Consumer and Industrial Products, Rev 80% 20% PA1 50% tPLH 80% 50% 20% tTLH 50% tpv 50% Figure 6. Output Enable to Output Valid OVDD 80% 20% 0V PA1 VDD 50% 0V tPHL OVDD 80% 50% 20% 0V tTHL VDD 0 VDD OVDD Freescale Semiconductor ...
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... Output pad propagation tpo delay (high drive), 40%–60% Output pad propagation tpo delay (standard drive), 40%–60% i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Table 19. Slow I/O AC Parameters Test Min. Capacitance Rise/Fall — — 40 3.0–3 0.95/0.84 3.0– ...
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... V/ns 0.84/1.23 1.19/1.58 0.54/0.73 0.91/1.20 0.35/0.50 0.60/0.80 0.76/1.10 1.17/1.56 0.41/0.62 0.63/0.86 0.34/0.49 0.58/0/79 0.34/0.49 0.36/0.49 0.40/0.59 0.60/0.83 0.21/0.32 0.32/0.44 0.20/0.30 0.34/0.47 0.11/0.17 0.20/0.27 Freescale Semiconductor ...
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... Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 3 1.95 V (1.65–1.95 V range), and –40 °C. Input transition time from pad (20%–80%). 5. Hysteresis mode is recommended for input with transition time greater than 25 ns. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Test Min. Capacitance Rise/Fall 3.0– ...
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... V/ns 0.43/0.61 0.72/0.95 0.59/0.81 0.98/1.27 V/ns 0.34/0.50 0.56/0.72 0.40/0.55 0.66/0.87 V/ns 0.23/0.34 0.38/0.52 Freescale Semiconductor — ...
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... Table 21. Fast I/O AC Parameters for OVDD = 3.0 Parameter Duty Cycle Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Standard Drive) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Test Min. Symbol Condition Rise/Fall tdit ...
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... V/ns 1.26/1.70 1.78/2.39 V/ns 2 0.95/1.30 1.20/1.60 V/ns 0.63/0.87 108 250 mA/ns 113 262 82 197 mA/ 207 52 116 mA/ns 55 121 Freescale Semiconductor ...
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... Duty cycle Clock frequency Output pad transition times (max. drive) Output pad transition times (high drive) Output pad transition times (standard drive) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor tpi 1.6pF 0.729/0.458 0.97/0.0649 1.404/0.97 tpi 1.6pF 1.203/0.938 1.172/1.187 1.713/1.535 tpi 1 ...
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... V/ns 2 0.72/0.81 1.66/1.68 0.62/0.70 1.03/1.05 V/ns 0.33/0.37 0.75/0.77 0.31/0.35 0.51/0.53 V/ns 0.16/0.18 0.38/0.39 171 407 mA/ns 3 183 432 100 232 mA/ns 106 246 50 116 mA/ns 52 123 0.11/0.13 0.16/0. 1.22/1.45 1.89/2.21 ns 2.04/2.27 2.69/3.01 ns Freescale Semiconductor ...
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... Output enable to output valid delay (max. drive), 50%–50% Output enable to output valid delay (high drive), 50%–50% Output enable to output valid delay (standard drive), 50%–50% i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Load Min. Symbol Condition Rise/Fall Fduty — ...
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... V/ns 2 0.52/0.61 0.90/1.02 0.51/0.63 091/1.06 V/ns 0.36/0.42 0.63/0.67 0.37/0.44 0.65/0.72 V/ns 0.23/0.26 0.39/0.40 171 426 mA/ns 3 183 450 82 233 mA/ns 87 245 43 115 mA/ns 46 120 0.11/0.13 0.16/0. 1.40/1.34 2.25/2.16 ns 2.22/2.16 3.06/2.97 ns Max. Units OVDD+0.3 V 0.2 OVDD V OVDD+0.6 V OVDD+0.6 V Freescale Semiconductor ...
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... Output enable to output valid delay (max. drive), 40%–60% Output enable to output valid delay (high drive), 40%–60% Output enable to output valid delay (standard drive), 40%–60% i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Table 25. AC Parameters for SDRAM I/O Load Min. Symbol Condition Rise/Fall Fduty — ...
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... Max. Typ. Units Notes Rise/Fall — — 125 MHz 1 1.14/1.13 1.62/1. 2.13/2.09 3.015/2.7 7 1.71/1.68 2.39/2.22 ns 3.22/3.12 4.53/4.16 3.38/3.27 4.73/4.38 ns 6.38/6.23 9.05/8.23 Freescale Semiconductor ...
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... Output enable to output valid delay (standard drive), 40%–60% Output pad slew rate (max. drive) Output pad slew rate (high drive) Output pad slew rate (standard drive) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Load Min. Symbol Condition Rise/Fall ...
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... Max. Typ. Units Notes Rise/Fall — — 133 MHz — 0.80/0.72 1.19/1. 1.49/1.34 2.21/1.90 1.56/1.70 2.52/2. 2.07/2.19 3.29/3.24 1.60/1.75 2.49/2. 2.00/2.14 3.11/3.10 2.17/1.81 3.35/2. 2.56/2.29 3.35/2.54 2.13/1.86 3.38/2. 2.62/2.23 4.14/2.38 1.35/1.5 2.15/2.19 V/ns 2 0.72/0.81 1.12/1.16 Freescale Semiconductor ...
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... Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1 and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core (20%–80%). i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Load Min. ...
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... OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) 1-Wire Memory Device OW2 OW3 OW1 Figure 7. 1-Wire RPP Timing Diagram Max. OVDD + 0.3 OVDD/2 – 0.25 0.5 OVDD + 0.6 OVDD/2 + 0.175 OVDD/2 + 0.125 “Presence Pulse” OW4 Freescale Semiconductor Units ...
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... OW6 Transmission Time Slot Figure 9 and Figure 10 show write 1 and read sequence timing, respectively. parameters (OW7–OW8) that are shown in the figure. 1-Wire bus (OWIRE_LINE) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Symbol t RSTL t PDH t PDL t RSTH Table 31 describes the timing parameters (OW5– ...
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... Applications Processor for Consumer and Industrial Products, Rev OW8 OW7 OW9 Figure 10. Read Sequence Timing Diagram Table 32. WR1 /RD Timing Parameters Symbol t LOW1 t SLOT t RELEASE Table 33. Timing Parameters Description Min. Typ. Max. Units 117 120 15 — 45 Value/Contributing Factor Peripheral clock frequency 5.0 ns 4.6 ns 12.0 ns 8.5 ns 8 Freescale Semiconductor ...
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... PIO Mode Timing Parameters Figure 11 shows a timing diagram for PIO read mode. ADDR (See note 1) READ Data(15:0) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Table 33. Timing Parameters (continued) Description t1 t2r DIOR tA IORDY IORDY Figure 11. PIO Read Mode Timing ...
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... T – (tskew1 + tskew2 + tskew6) T – (tsu + thi) T > tsu + thi + tskew3 + tskew4 T t1 t2w DIOR DIOW ton tA IORDY IORDY Figure 12. PIO Write Mode Timing Adjustable Parameter time_1 time_2r time_9 If not met, increase time_2 — time_ax time_pio_rdx time_1, time_2r, time_9 toff t1 Freescale Semiconductor Table 34 ...
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... MDMA read and write modes, respectively. DMARQ ADDR (See note 1) DMACK DIOR READ Data(15:0) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Relation T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew5) T – (tskew1 + tskew2 + tskew6) T – (tskew1 + tskew2 +tskew5) T – tskew1 T ...
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... T – (tskew1 + tskew2 + tskew6) T – (tsu + tco + 2 T – (tskew1 + tskew2 + tskew6) T – tskew1 T – tskew1 T). tk1 tkjn toff Table 36 for details Adjustable Parameter(s) time_m time_d time_k time_d, time_k time_d — time_d time_k tbuf + 2 tcable2) time_d, time_k time_jn — Freescale Semiconductor 3 ...
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... UDMA in-transfer. ADDR DMARQ DMACK DIOR DIOW IORDY DATA READ DATA WRITE buffer_en Figure 16. Timing for Host-Terminated UDMA In-Transfer i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor tack ADDR DMARQ DMACK tenv DIOR DIOW tc1 IORDY DATA READ tds ...
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... T) – (tco + tsu + tbuf + 2 tcable2) > trfs (drive – (tskew1 + tskew2) T) – (tskew1 + tskew2) T – tskew1 T – tskew1 tack ton tdzfs tcvh toff Required Conditions time_ack time_env tskew3, ti_ds, ti_dh should be low enough T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh — Freescale Semiconductor ...
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... UDMA out-transfer. ADDR DMARQ DMACK DIOW DIOR DATA WRITE IORDY buffer_en Figure 19. Timing for Host-Terminated UDMA Out-Transfer i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor tack tenv tcyc tcyc ton tdzfs tdvs tdvh tdvs tli1 tack tss tcyc ...
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... T – (tskew1 + tskew2 tsui + tco + tbuf + tbuf T – (tskew1) T – (tskew1 + tskew2) T – (tskew1 + tskew2) T) – (tskew1 + tskew2) T – tskew1 T – tskew1 Timing.” How to Meet? time_ack time_env time_dvs time_dvh time_cyc time_cyc — time_dzfs time_ss — — — — time_cvh — Freescale Semiconductor ...
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... Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge VSYNC HSYNC PIXCLK DATA[15:0] Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor ...
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... Symbol tVSYNC tDsu tDh tCLKh tCLKl fCLK Min. Max. Units 67.5 — 1 — 1 — 1.2 — 10 — 10 — — 48 10% MHz describes the timing parameters P6 P5 Min. Max. Units 67.5 — 1 — 1.2 — 10 — 10 — — 48 10% MHz Freescale Semiconductor ...
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... Figure 23. CSPI Master Mode Timing Diagram SS n (input) t6’ SCLK (input) t10 t11 MISO t12 t13 MOSI Figure 24. CSPI Slave Mode Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor t2 t1 t2’ t1’ Table t7’ t5’ t3’ ...
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... T — per 2T — sclk 30 — per per 0 — — clkoL clkoH – clkiL clkiH 5 T ipg — clkoL clkoH clkiL clkiH T + 0.5 — ipg 0 — 0 — Freescale Semiconductor Units — — — — — ns — ns — — ...
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... SDRAM clock low-level width SD3 SDRAM clock cycle time SD4 CS, RAS, CAS, WE, DQM, CKE setup time SD5 CS, RAS, CAS, WE, DQM, CKE hold time i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor SD1 SD4 SD5 SD4 SD5 SD5 SD7 ...
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... Table 42. DDR/SDR SDRAM Read Cycle Timing Parameters (continued) ID SD6 Address setup time SD7 Address hold time SD8 SDRAM access time i.MX25 Applications Processor for Consumer and Industrial Products, Rev Parameter Symbol Min. Max. tAS 2.0 — tAH 1.8 — tAC — 6.47 Freescale Semiconductor Unit ...
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... SDCLK SDCLK CS RAS CAS SD4 WE SD6 ADDR BA DQ DQM Figure 26. SDR SDRAM Write Cycle Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Parameter SD1 SD3 SD11 SD5 SD12 SD7 ROW / BA Symbol Min. Max. tOH 1.2 — ...
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... SD2 SD3 SD10 ROW/BA Freescale Semiconductor Unit clock clock ns ns ...
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... ADDR BA CKE Don’t care Figure 28. SDRAM Self-Refresh Cycle Timing Diagram The clock continues to run unless CKE is low. Then the clock is stopped in low state. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Symbol tCH tCL tCK tAS tAH 1 ...
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... SD18 SD17 Data Data Data Data SD17 SD18 Parameter Min. Max. Unit 1.8 — SD20 SD19 SD18 Data Data Data Data SD18 1 Symbol Min. Max. tDS 0.95 — tDH 0.95 — tDSS 1.8 — tDSH 1.8 — Freescale Semiconductor ns Unit ...
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... SD21 DQS – DQ Skew (defines the data valid window in read cycles related to DQS) SD22 DQS DQ HOLD time from DQS SD23 DQS output access time from SDCLK posedge i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor SD22 SD21 Data ...
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... DDR3 SDRAM clock cycle time i.MX25 Applications Processor for Consumer and Industrial Products, Rev DDR1 DDR4 DDR3 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Table Parameter DDR2 49, “tlS, tlH Derating Values for DDR2-400 Symbol Min. Max. t 0.45 0. 0. Freescale Semiconductor Unit ...
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... Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Parameter CK, CK Differential Slew Rate 1.5 V/ns tlH tlS +94 +217 +124 +89 +209 +119 +83 +197 +113 +75 ...
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... Max. t 0.025 — DS1(base) t 0.025 — DH1(base) t 0.2 — DSS t 0.2 — DSH t -0.25 0.25 DQSS t 0.35 — DQSH t 0.35 — DQSL Table 51, “DtDS1, 1,2,3 0.7 V/ns 0.6 V/ns 0.5 Vns Freescale Semiconductor Unit ns ns tCK tCK tCK tCK tCK 0.4 V/ ...
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... DDR26 DQS output access time from SDCLK posedge 1 Test conditions are at capacitance=15 pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for address and controls. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor DQS Single-Ended Slew Rate 63 — — ...
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... NFIO[7:0] Figure 35. Address Latch Cycle Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address Figure 34 through NF4 Freescale Semiconductor ...
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... Figure 37. Read Data Latch Cycle Timing Diagram ID Parameter NF1 NFCLE setup time NF2 NFCLE hold time NF3 NFCE setup time NF4 NFCE hold time i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 ...
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... N/A tDHR N/A NOTE Table 54 describes the timing parameters Example Timing for NFC Clock 33 MHz Unit Min. Max. 28 — — — — 27.5 ns 620 — — — ns 12.5 — — — ns Freescale Semiconductor ...
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... WE4 Clock fall to address valid WE5 Clock rise/fall to address invalid WE6 Clock rise/fall to CSx_B valid WE7 Clock rise/fall to CSx_B invalid i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor WEIM Output Timing WE1 WE2 ... WE4 WE6 WE8 WE10 WE12 ...
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... Recommended drive strength for all controls, address and BCLK is maximum drive. i.MX25 Applications Processor for Consumer and Industrial Products, Rev (continued) Parameter NOTE Min. Max. Unit 3 — ns (BCLK/2) + — ns 2.63 6.9 — — ns 2.4 — — ns 7.2 — — — ns 5.4 — ns –3.2 — ns Freescale Semiconductor ...
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... ADDR Last Valid Address CS[x] RW LBA OE EB[y] DATA Figure 40. Synchronous Memory Timing Diagram for Write Access— i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Table 54 for specific control parameter settings. WE4 V1 WE6 WE14 WE10 WE12 WE19 WE4 ...
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... WE22 WE22 WE19 WE19 V1 V1+2 Halfword Halfword WE18 WE18 WSC=2, SYNC=1, DOL=0 Address V1 WE15 WE24 WE22 WE17 V1 WE16 BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1 WE5 Address V2 WE7 WE11 WE13 V2 V2+2 Halfword Halfword WE5 WE7 WE9 WE13 WE17 V1+4 V1+8 V1+12 Freescale Semiconductor ...
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... M_DATA WE6 CS[x] RW LBA OE WE12 EB[y] Figure 44. Muxed A/D Mode Timing Diagram for Synchronous Read Access— i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor WE5 Address V1 WE16 Write WE15 WSC=7, LBA=1, LBN=1, LAH=1 WE5 Address V1 WE14 WE15 ...
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... Applications Processor for Consumer and Industrial Products, Rev Table 55 help to determine timing parameters relative to chip select (CS) WE31 Address V1 WE39 WE35 WE37 V1 WE43 MAXDI WE31 Addr. V1 WE32A WE40 WE39 WE35A WE37 WE32 Next Address WE40 WE36 WE38 WE44 D(V1) WE44 WE36 WE38 Freescale Semiconductor ...
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... EB[y] DATA Figure 47. Asynchronous Memory Write Access CS[x] ADDR/ M_DATA RW LBA OE EB[y] Figure 48. Asynchronous A/D Mux Write Access i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE31 D(V1) Addr. V1 WE32A WE33 ...
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... CSA) –3 + (OEA + 3 + (OEA + RLBN + RLBN + RLBA + RLBA + ADH + 1 – ADH + 1 – CSA) CSA) — 3 – (OEN – CSN) 4 — (RBEA – CSA) 5 — 3 – (RBEN – CSN) — (LBA – CSA) — 3 – CSN Freescale Semiconductor Unit ...
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... DATA maximum delay from chip input data to its internal FF. 9 DTACK maximum delay from chip dtack input to its internal FF. Note: All configuration parameters (CSA,CSN,WBEA,WBEN,LBA,LBN,OEN,OEA,RBEA & RBEN) are in cycle units. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Determination By Synchronous Measured 1 Parameters WE14 – ...
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... Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. i.MX25 Applications Processor for Consumer and Industrial Products, Rev first bit Figure 50. ESAI Transmit Timing 83 87 last bit 88 91 See Note Freescale Semiconductor ...
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... FSR (bit) out FSR (word) out Data in FSR (bit) in FSR (word) in Flags in Figure 52 shows the ESAI HCKT timing diagram. HCKT SCKT (output) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor first bit Figure 51. ESAI Receive Timing Diagram 95 96 Figure 52 ...
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... Transmit high-frequency clock Receive high-frequency clock Symbol Expression SSICC — — — 9.0 — — 9.0 — Table 56 and Table 57 describe Comments 3 Min. Max. Condition 30.0 — 30.0 — — — — 6 — 15 — — — 6 — 15 — — Freescale Semiconductor Unit ...
Page 83
... SCKT rising edge to FST out (wl) high 83 SCKT rising edge to FST out (wl) low 84 SCKT rising edge to data out enable from high impedance 85 SCKT rising edge to transmitter #0 drive enable assertion i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor 3 Symbol Expression — — — — 5 — ...
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... Min. Max. Condition Unit — 18 — 13 — 21 — 16 — 14 — 9 2.0 — 18.0 — 2.0 — 18.0 — 4.0 — 5.0 — — 21.0 — ns — 14.0 — ns — 14 — 9 — — ns — 18.0 — ns — 18.0 — ns Table 59: Freescale Semiconductor ...
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... In normal-speed mode for MMC card, clock frequency can be any value between MHz. In high speed mode, clock frequency can be any value between MHz satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor SD4 SD2 SD5 CLK ...
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... FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode. i.MX25 Applications Processor for Consumer and Industrial Products, Rev Table 60 describes the timing parameters (M1–M4) shown Table 60. MII Receive Signal Timing 1 M4 Min. Max. Unit 5 — — ns 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period Freescale Semiconductor ...
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... MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL) Figure 57 shows MII asynchronous input timings. the figure. FEC_CRS, FEC_COL Figure 57. MII Async Inputs Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Table 61 describes the timing parameters (M5–M8) shown Table 61. MII Transmit Signal Timing ...
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... Applications Processor for Consumer and Industrial Products, Rev Min. 1.5 Table 63 describes the timing parameters (M10—M15) M14 M15 M10 M11 M12 M13 Min. 0 — 40% 40% Max. Unit — FEC_TX_CLK period Max. Unit — — ns — ns 60% FEC_MDC period 60% FEC_MDC period Freescale Semiconductor ...
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... M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid M20 FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to REF_CLK setup M21 REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Table 64 describes the timing parameters (M16–M21) shown in the M16 M18 M19 M20 M21 Table 64 ...
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... Applications Processor for Consumer and Industrial Products, Rev Table 65. Tx Pin Characteristics Symbol Min. Typ. 2 — — 0.8 OL Table 66. Rx Pin Characteristics Symbol Min. Typ. 1 0.8 Vcc — — 0 OFFTXD 0. ONRXD OFFRXD Figure 60. FlexCAN Timing Diagram Max. Units 1 Vcc + 0.3 V — V Max. Units 1 Vcc V — Freescale Semiconductor ...
Page 91
... Figure 63. Timing Diagram for FlexCAN Shutdown-to-Standby Signal Because integer multiples are not possible, taking into account the range of frequencies at which the SoC has to operate, DPLLs work in FOL mode only. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor V x 0.75 CC ...
Page 92
... C module timing IC9 IC3 STOP START Standard Mode Fast Mode Min. Max. Min. Max 2.5 4.0 - 0.6 4 3.45 0 0.9 4.0 - 0.6 4.7 - 1.3 4.7 - 0.6 3 250 - 100 4 1000 20+0.1C 300 300 20+0.1C 300 b - 400 - 400 Freescale Semiconductor START Unit ...
Page 93
... A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Parameter ) b Standard Mode Unit Min ...
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... Wait between HSYNC and VSYNC rising edge T6 Wait between last data and HSYNC rising edge pixel clock period i.MX25 Applications Processor for Consumer and Industrial Products, Rev Description Table 69 Line n Line 1 T6 Min. Max. 22.5 1000 1 — 5 — 5 — 2 — 1 — Freescale Semiconductor and Unit ...
Page 95
... The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse width modulator output (PWMO) external pin. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor T4 Figure 66. LCDC TFT Mode Timing Diagram Description Table 71 lists the PWM timing characteristics ...
Page 96
... ISO/IEC 7816 defines reset and power-down sequences (for detailed information see ISO/IEC 7816). i.MX25 Applications Processor for Consumer and Industrial Products, Rev Figure 67. PWM Timing Table 71. PWM Output Timing Parameter Minimum 1 0 12.29 9.91 — — — 8. Maximum Unit ipg_clk MHz — ns — ns 0.5 ns 0.5 ns 9.37 ns — ns Freescale Semiconductor ...
Page 97
... SIM RST rise time / fall time (SIMx_RSTy) 1 50% duty cycle clock, 2 With With With Cin = 30 pF, Cout = 30 pF, 5 With Cin = 30 pF, i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor 1 /SI1 SI3 SI4 SI5 SI6 Figure 68. SIM Clock Timing Diagram Symbol ...
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... SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1. i.MX25 Applications Processor for Consumer and Industrial Products, Rev RESPONSE Min. Max. — 200 400 40,000 Units clk cycles clk cycles Freescale Semiconductor ...
Page 99
... SIMx_DATAy_RX_TX is negated • SIMx_SVENy is negated Each of the above steps requires one CKIL period (usually 32 kHz). Power-down may be initiated by a SIM card removal detection may be launched by the processor. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor 3 T1 Min. Max. — ...
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... SJC timing parameters (SJ1–SJ13) indicated in the SJ1 SJ2 VM VIL Figure 72. Test Clock Input Timing Diagram Min. Max. 0.9 1/Fckil 1.1 1/Fckil 1.8 1/Fckil 2.2 1/Fckil 2.7 1/Fckil 3.3 1/Fckil 0.9 1/Fckil 1.1 1/Fckil SJ2 VM SJ3 Freescale Semiconductor Unit ...
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... TDO (Output) TDO (Output) TDO (Output) Figure 74. Test Access Port Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid SJ8 Input Data Valid ...
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... Applications Processor for Consumer and Industrial Products, Rev. 6 102 SJ13 Figure 75. TRST Timing Diagram Table 76. SJC Timing Parameters All Frequencies Unit Min. Max. 1 100 — 40 — — — 50 — — 50 — — 50 — — 44 — 44 100 — 40 — Freescale Semiconductor ...
Page 103
... RS LCD_CS LCD_CLK (LCD_DATA[6]) SDATA (LCD_DATA[7]) RS Figure 76. SLCDC Timing Diagram—Serial Transfers to LCD Device i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor tcss tcyc tds MSB trss RS=0 => command data, RS=1=> display data (This diagram shows the case SCKPOL = 1, CSPOL = 0) ...
Page 104
... CSPOL=0) trss trsh tcyc tds tdh command data display data (This diagram shows the case CSPOL=1) Typ. Max. Units — — ns — — ns — 2641 ns — — ns — — ns — — ns — — ns — — ns — — ns Freescale Semiconductor ...
Page 105
... AUDn_TXC (Output) AUDn_TXFS (bl) (Output) AUDn_TXFS (wl) (Output) AUDn_TXD (Output) AUDn_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 78. SSI Transmitter with Internal Clock Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Min prop ( cyc prop ( cyc prop (t ...
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... Min. Max. Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns 10.0 — ns 0.0 — ns — 25.0 pf Freescale Semiconductor ...
Page 107
... CK high to FS (wl) low SS20 SRXD setup time before (Rx) CK low SS21 SRXD hold time after (Rx) CK low SS47 Oversampling clock period i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor SS1 SS5 SS4 SS9 SS11 SS20 SS51 SS47 ...
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... Applications Processor for Consumer and Industrial Products, Rev. 6 108 Parameter SS22 SS25 SS26 SS27 SS31 SS37 SS44 Min. Max. 6.0 — — 3.0 6.0 — — 3.0 Table 81 describes the timing SS24 SS29 SS33 SS39 SS38 SS45 SS46 Freescale Semiconductor Unit ...
Page 109
... For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation). i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Parameter External Clock Operation Synchronous External Clock Operation Min ...
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... External Clock Operation Table 82 describes the timing parameters SS24 SS34 SS41 SS36 Min. Max. 81.4 — 36.0 — — 6.0 36.0 — — 6.0 –10.0 15.0 10.0 — –10.0 15.0 10.0 — — 6.0 — 6.0 10.0 — 2.0 — Freescale Semiconductor Unit ...
Page 111
... With a 250fF load edge (teoc) Valid data out delay after With a 250fF load eoc rise edge (tdata) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Conditions ADC — Analog Bias — Timing Characteristics — ...
Page 112
... Conditions Power Supply Requirements — — Touchscreen Interface — 3 Conversion Characteristics — Min. Typ. Max. Unit — — 2.1 mA 0.5 mA — — 100 — 1500 — — 10 — +/–0.75 — LSB — +/–2.0 — LSB — — +/–2 %FS Freescale Semiconductor ...
Page 113
... Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Figure 82. Start-up Sequence st ). The best way to guarantee this is to make the input multiplexer ...
Page 114
... ADC operation, including the idle cycles. If the conditions are not met power is lost during ADC operation, then a new start-up sequence is required for ADC to become operational again. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 114 Freescale Semiconductor ...
Page 115
... UA1 Start TXD Bit 0 Bit 1 Bit (output) Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor UA1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Possible Parity Bit ...
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... Possible Parity Bit Next Start STOP Bit 6 Bit 7 Par Bit Bit BIT UA2 UA2 Min. Max. 2 – 1/(16 1/F + 1/(16 baud_rate baud_rate baud_rate baud_rate UA4 UA3 UA3 Possible Bit 5 Bit 6 Bit 7 Parity Bit Freescale Semiconductor Units — Units — STOP BIT ...
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... DAT_SE0 unidirectional, 6-wire mode • VP_VM bidirectional, 4-wire mode • VP_VM unidirectional, 6-wire mode The following subsections describe the timings for these four modes. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Symbol Min 1/F – T TIRbit ...
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... Applications Processor for Consumer and Industrial Products, Rev. 6 118 Transmit enable, active low Tx data when USB_TXOE_B is low Differential Rx data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 Rx indicator when USB_TXOE_B is high US1 US4 US7/US8 Signal Description US2 US6 Freescale Semiconductor ...
Page 119
... USB_RCV Figure 91 shows the USB transmit waveform in DAT_SE0 unidirectional mode diagram. Transmit USB_DAT_VP USB_SE0_VM Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Signal Name Direction Min. USB_DAT_VP Out USB_SE0_VM Out USB_TXOE_B ...
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... Tx VP data when USB_TXOE_B is low In (Rx) • data when USB_TXOE_B is high Out (Tx) • data when USB_TXOE_B low In (Rx) • data when USB_TXOE_B high In • Differential Rx data US14 Condition/ Max. Unit Reference Signal 51.0 % — 8.0 ns USB_TXOE_B 10.0 ns USB_TXOE_B Signal Description Freescale Semiconductor ...
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... Tx rise/fall time US21 Tx duty cycle US22 Tx high overlap US23 Tx low overlap US24 Enable delay US25 Disable delay i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor US4 US2 US5 Signal Name Direction Min. USB_DAT_VP Out — USB_SE0_VM Out — ...
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... Tx VP data when USB_TXOE_B is low Out Tx VM data when USB_TXOE_B is low data when USB_TXOE_B is high data when USB_TXOE_B is high In Differential Rx data US30 US34 Condition/ Max. Unit Reference Signal — 3.0 ns — 3.0 ns +4.0 ns USB_SE0_VM +2.0 ns USB_DAT_VP Signal Description US32 US31 Freescale Semiconductor ...
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... Tx low overlap US36 Enable delay US37 Disable delay US38 Rx rise/fall time US39 Rx rise/fall time US40 Rx skew US41 Rx skew i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor US38 US40 US39 US41 Signal Direction Min. USB_DAT_VP Out — USB_SE0_VM Out — ...
Page 124
... Dimensioning and tolerancing per ASME Y14.5M-1994. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 124 Signal Description Table 97 US16 US16 US17 US17 Min. Max. — 6.0 — 0.0 — 9.0 describes the timing Conditions/ Unit Reference Signal Figure 98: Freescale Semiconductor ...
Page 125
... Table 98 Package Ground, Power Sense, and Reference Contact Assignments Contact Name BATT_VDD P10 FUSE_VDD T17 MPLL_GND U17 MPLL_VDD U18 NGND_ADC Y13 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor 17 17 i.MX25 Production Package zzxz Contact Assignment 125 ...
Page 126
... G11, J8, J12, K6, K7, K12, M5, M6, M7, N8, P8, P9 REF V11 UPLL_GND M16 UPLL_VDD L16 USBPHY1_UPLLVDD M17 USBPHY1_UPLLVSS N17 USBPHY1_VDDA K16 USBPHY1_VDDA_BIAS K19 USBPHY1_VSSA L19 USBPHY1_VSSA_BIAS J17 USBPHY2_VDD W18 USBPHY2_VSS W17 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 126 Contact Assignment Freescale Semiconductor ...
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... D7 A19 A4 A20 B6 A21 C7 A22 A5 A23 A6 A24 B7 A25 A7 SD0 A12 SD1 C13 SD2 B13 SD3 D14 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Contact Signal Name Assignment NFWE_B G4 NFRE_B C1 NFALE F4 NFCLE E4 NFWP_B H4 NFRB C2 D15 J2 D14 J1 D13 H2 D12 H3 D11 ...
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... U20 VSTBY_REQ R18 VSTBY_ACK T20 POWER_FAIL T19 RESET_B T18 POR_B U19 CLKO V20 BOOT_MODE0 V19 BOOT_MODE1 W20 CLK_SEL W19 TEST_MODE V18 OSC24M_EXTAL Y15 OSC24M_XTAL Y16 OSC32K_EXTAL Y11 OSC32K_XTAL Y10 TAMPER_A N10 TAMPER_B N11 MESH_C P11 MESH_D P12 OSC_BYP Y12 Freescale Semiconductor ...
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... Table 100 Package i.MX25 No Connect Contact Assignments Signal Name NC_BGA_B20 NC_BGA_E17 NC_BGA_H17 NC_BGA_J19 NC_BGA_M18 NC_BGA_P20 NC_BGA_U15 NC_BGA_U16 NC_BGA_V15 NC_BGA_V16 NC_BGA_V17 NC_BGA_W14 NC_BGA_Y2 NC_BGA_Y14 NC_BGA_Y17 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Contact Signal Name Assignment UART1_TXD U1 UART1_RTS T3 UART1_CTS T2 UART2_RXD P4 UART2_TXD T1 UART2_RTS R3 UART2_CTS R2 ...
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... Package Ball Map Table 101 shows the i.MX25 17 17 package ball map. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 130 Table 101. i.MX25 17 17 Package Ball Map Freescale Semiconductor ...
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... Table 101. i.MX25 17 17 Package Ball Map (continued) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor 131 ...
Page 132
... Table 101. i.MX25 17 17 Package Ball Map (continued) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 132 Freescale Semiconductor ...
Page 133
... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. • Parallelism measurement shall exclude any effect of mark on package’s top surface. Figure 99 i.MX25 Production Package i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Figure 99: 133 ...
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... G7, G13, H7, H13, H18, J18, N7, N8, R10, R15, R16, T9, T10, V10, REF AA14 UPLL_GND N16 UPLL_VDD M18 UPLL_BYPCLK U21 USBPHY1_UPLLVDD L21 USBPHY1_UPLLVSS M19 USBPHY1_VDDA K15, K16 USBPHY1_VDDA_BIAS L22 USBPHY1_VSSA K19 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 134 Contact Assignment Freescale Semiconductor ...
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... A10 B5 A11 C21 A12 B22 A13 D21 A14 A4 A15 D6 A16 A5 A17 E6 A18 A6 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Contact Assignment Ball Name Ball Position A23 E9 A24 B7 A25 D8 BCLK A8 BOOT_MODE0 AA22 BOOT_MODE1 W21 CAS B16 CLK0 Y22 ...
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... PWM W4 RAS D15 RW D5 RESET_B U19 RTCK W13 SD0 A13 SD1 D12 SD2 B12 SD3 A14 SD4 B13 SD5 A15 SD6 B11 SD7 A12 SD8 D10 SD9 A10 SD10 A11 SD11 B10 SD12 B9 SD13 E11 SD14 B8 SD15 D9 SDBA0 A17 Freescale Semiconductor ...
Page 137
... SJC_MOD AB11 Table 104 lists the package i.MX25 no connect contact assignments. Table 104 Package i.MX25 No Connect Contact Assignments Signal Name NC_BGA_E4 NC_BGA_L4 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Ball Name Ball Position NFRB G5 NFRE_B C1 NFWE_B E1 NFWP_B ...
Page 138
... Package Ball Map Table 101 shows the i.MX25 12 12 package ball map. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 138 Table 105. i.MX25 12 12 Package Ball Map Freescale Semiconductor ...
Page 139
... Table 105. i.MX25 12 12 Package Ball Map (continued) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor 139 ...
Page 140
... Table 105. i.MX25 12 12 Package Ball Map (continued) i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 140 Freescale Semiconductor ...
Page 141
... Table • Updated • Updated values in • Updated 0 6/2009 Initial release. i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6 Freescale Semiconductor Table 106. Revision History Revision Table 54, "WEIM Bus Timing Parameters," on page 71 Table 6, "DC Operating Conditions," on page 11 Table 1, “ ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...