MCIMX253CJM4A Freescale, MCIMX253CJM4A Datasheet - Page 88
MCIMX253CJM4A
Manufacturer Part Number
MCIMX253CJM4A
Description
Manufacturer
Freescale
Datasheet
1.MCIMX253CJM4A.pdf
(142 pages)
Specifications of MCIMX253CJM4A
Lead Free Status / RoHS Status
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1
3.7.9.2
The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3
standard MII specification. However the FEC can function correctly with a maximum MDC frequency of
15 MHz.
Figure 58
shown in the figure.
88
M10
M11
M12
M13
M14
M15
M9
FEC_COL has the same timing in 10-Mbit 7-wire interface mode.
1
ID
ID
FEC_MDIO (output)
FEC_MDC (output)
FEC_MDIO (input)
FEC_MDC falling edge to FEC_MDIO output invalid (min.
propagation delay)
FEC_MDC falling edge to FEC_MDIO output valid (max.
propagation delay)
FEC_MDIO (input) to FEC_MDC rising edge setup
FEC_MDIO (input) to FEC_MDC rising edge hold
FEC_MDC pulse width high
FEC_MDC pulse width low
FEC_CRS to FEC_COL minimum pulse width
shows MII asynchronous input timings.
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
Figure 58. MII Serial Management Channel Timing Diagram
Table 62. MII Asynchronous Inputs Signal Timing
Table 63. MII Serial Management Channel Timing
Characteristic
Characteristic
M12
M13
Table 63
M14
describes the timing parameters (M10—M15)
Min.
1.5
Min.
40%
40%
M10
18
—
0
0
M11
M15
Max.
—
Max.
60%
60%
—
—
—
5
FEC_TX_CLK period
Freescale Semiconductor
FEC_MDC period
FEC_MDC period
Unit
Unit
ns
ns
ns
ns
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