MCIMX253CJM4A Freescale, MCIMX253CJM4A Datasheet - Page 72
MCIMX253CJM4A
Manufacturer Part Number
MCIMX253CJM4A
Description
Manufacturer
Freescale
Datasheet
1.MCIMX253CJM4A.pdf
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High is defined as 80% of signal value; low is defined as 20% of signal value.
BCLK parameters are being measured from the 50% point. For example, high is defined as 50% of signal value and low is
defined as 50% as signal value.
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE17
WE18
WE19
WE20
WE21
WE22
WE23
WE24
WE25
WE26
WE27
WE8
WE9
ID
Clock rise/fall to RW_B valid
Clock rise/fall to RW_B invalid
Clock rise/fall to OE_B valid
Clock rise/fall to OE_B invalid
Clock rise/fall to EBy_B valid
Clock rise/fall to EBy_B invalid
Clock rise/fall to LBA_B valid
Clock rise/fall to LBA_B invalid
Clock rise/fall to output data valid
Clock rise to output data invalid
Input data valid to clock rise, FCE=1
Input Data Valid to Clock rise, FCE=0 (in the case there is ECB_B asserted
during access)
Input Data Valid to Clock rise, FCE=0 (in the case there is NO ECB_B asserted
during access)
Clock rise to input data invalid, FCE=1
Clock rise to input data invalid, FCE=0
ECB_B setup time, FCE=1
ECB_B setup time, FCE=0
ECB_B hold time, FCE=1
ECB_B hold time, FCE=0
DTACK_B setup time
DTACK_B hold time
The test condition load capacitance was 25 pF. Recommended drive
strength for all controls, address, and BCLK is maximum drive.
Recommended drive strength for all controls, address and BCLK is
maximum drive.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
Table 54. WEIM Bus Timing Parameters
Parameter
NOTE
1
(continued)
(BCLK/2) +
Min.
17.5
2.63
–3.2
3.6
6.9
2.4
7.2
5.4
8
3
7
6
6
0
5
0
1
5
5
0
1
Freescale Semiconductor
Max.
11.5
5.5
2.5
12
12
10
20
10
—
—
—
—
—
—
—
—
—
—
—
8
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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