PPC440GX-3RF667C Applied Micro Circuits Corporation, PPC440GX-3RF667C Datasheet - Page 83

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PPC440GX-3RF667C

Manufacturer Part Number
PPC440GX-3RF667C
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of PPC440GX-3RF667C

Family Name
440GX
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
667MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.55/2.5V
Operating Supply Voltage (max)
1.6/2.7V
Operating Supply Voltage (min)
1.5/2.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
552
Package Type
CBGA
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PPC440GX-3RF667C
Manufacturer:
BROADCOM
Quantity:
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Part Number:
PPC440GX-3RF667C
Manufacturer:
AMCC
Quantity:
1 045
Revision 1.20 – June 9, 2009
DDR SDRAM Read Operation
The following examples of timing for DDR SDRAM read operations are based on the relationship between the
incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of
MemClkOut(0) relative to the PLB clock (T
The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the
PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be
programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set
in RDCT. The delay of Read Clock relative to the PLB clock (T
Clock delay is set to zero.
DDR SDRAM MemClkOut0 and Read Clock Delay
In operation, following the receipt of an address and read command from the PPC440GX, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GX using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
AMCC
Data Sheet
MemClkOut0(0)
Read Clock
PLB Clk
MD
) is provided.
T
T
T
T
MD
MD
RD
RD
T
440GX – Power PC 440GX Embedded Processor
T
RD
min =
max =
min =
max =
MD
567ps
1705ps
-6ps
183ps
RD
) shown below assumes the programmable Read
83

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