PPC440GX-3RF800C Applied Micro Circuits Corporation, PPC440GX-3RF800C Datasheet
PPC440GX-3RF800C
Specifications of PPC440GX-3RF800C
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PPC440GX-3RF800C Summary of contents
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... On-chip 256KB SRAM configurable as L2 Code store or Ethernet Packet store memory • Selectable processor:bus clock ratios (Refer to the Clocking chapter in the PPC440GX Embedded Processor User’s Manual for details) • Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 166MHz (200MHz for 800MHz Rev F parts) • ...
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Power PC 440GX Embedded Processor Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Revision 1.19 – December 19, 2008 Data Sheet Figures PPC440GX Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 25mm, 552-Ball Ceramic (CBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 25mm, 552-Ball Plastic (FC-PBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Heat Sink Attached With Spring Clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Heat Sink Attached With Adhesive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DDR SDRAM Simulation Signal Termination Model ...
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... PPC440GX PPC440GX-3RF400C PPC440GX PPC440GX-3RF533C PPC440GX PPC440GX-3RF533CZ PPC440GX PPC440GX-3RF533E PPC440GX PPC440GX-3RF667C PPC440GX PPC440GX-3RF667CZ PPC440GX PPC440GX-3RF800C PPC440GX PPC440GX-3RF800CZ 4 Revision 1.19 – December 19, 2008 Processor Package Frequency 533MHz 25mm, 552 CBGA 667MHz 25mm, 552 CBGA 400MHz 25mm, 552 CBGA 533MHz 25mm, 552 CBGA 533MHz ...
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... The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PPC440GX User’s Manual for details on accessing these registers. Order Part Number Key ...
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... OPB interfaces up to 83.33MHz, 333MB/s Address Maps The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various address regions which the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440GX processor through the use of mtdcr and mfdcr instructions ...
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Revision 1.19 – December 19, 2008 Data Sheet System Memory Address Map Function DDR SDRAM SRAM 1 Local Memory Reserve IMU EBC Reserved UART0 Reserved UART1 Reserved IIC0 Reserved IIC1 Reserved OPB Arbiter Reserved Internal Peripherals GPIO Controller Ethernet PHY ...
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Power PC 440GX Embedded Processor System Memory Address Map Function Reserved PCI-X I/O Reserved PCI-X External Configuration Registers PCI-X Reserved PCI-X Bridge Core Configuration Registers Reserved PCI-X Special Cycle PCI-X Memory Notes: on-chip 1. DDR SDRAM and SRAM ...
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Revision 1.19 – December 19, 2008 Data Sheet DCR Address Map 4KB of Device Configuration Registers Function 1 Total DCR Address Space By function: Reserved Clocking Power On Reset System DCRs Memory Controller External Bus Controller External Bus Master I/F ...
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Power PC 440GX Embedded Processor PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, ISCSI, routers, switches, printers, set-top boxes, etc the first processor core to implement the ...
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Revision 1.19 – December 19, 2008 Data Sheet • OPB - Dynamic bus sizing 32-, 16-, and 8-bit data path - 36-bit address - 83.33MHz, maximum 333MB/s • DCR - 32-bit data path - 10 bit address On-Chip SRAM Features ...
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Power PC 440GX Embedded Processor • Simple message passing capability • Asynchronous to the PLB • PCI Power Management 1.1 • PCI register set addressable both from on-chip processor and PCI device sides • Ability to boot from ...
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... Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control Ethernet Controller Interface Ethernet support provided by the PPC440GX interfaces to the physical layer, but the PHY is not included on the chip. Features include: • One to four 10/100 interfaces running in full- and half-duplex modes ...
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Power PC 440GX Embedded Processor • Support for peripherals running on slower frequency buses Serial Port Features include: • One 8-pin UART and one 4-pin UART interface provided • Selectable internal or external serial clock to allow wide ...
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Revision 1.19 – December 19, 2008 Data Sheet Universal Interrupt Controller (UIC) Four Universal Interrupt Controllers (UIC) are available. They provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip PowerPC processor. Note: ...
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Power PC 440GX Embedded Processor 25mm, 552-Ball Ceramic (CBGA) Package Top View A1 Corner 1 A Lot Number AD Notes: 1. All dimensions are in mm. Bottom View ...
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... P 25 AMCC 440GX – Power PC 440GX Embedded Processor 24 ® PPC440GX Part Number 3xxfffx AAAAAAAA 2. Available in lead-free, RoHS compliant version. 25.0 23 0.66 ± 0.1 Solderball x 552 1.214 Ref 1.00 Typ 1 ± 0.3 23.0 7.5 0.5 ± 0.1 0.508 Ref 3.191 ± 0.17 17 ...
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Power PC 440GX Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DMAAck0 DMAAck1 DMAAck2[GMCRxD0, GMC0RxD0, TBIRxD0, RTBI0RxD0] DMAAck3[GMCRxD1, GMC0RxD1, TBIRxD1, RTBI0RxD1] DMAReq0 DMAReq1 DMAReq2[GMCRxDV, GMC0RxCtl, TBIRxD8, RTBI0RxD4] DMAReq3[GMCTxEn, GMC0TxCtl, ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCCD, EMC1RxErr, GMCGTxClk, GMC0TxClk, TBITxClk, RTBI0TxClk EMCCrS, EMC0CrSDV, GMCTxD7, GMC1TxD3, TBITxD7, RTBI1TxD3 EMCMDClk EMCMDIO EMCRxClk, GMCTxD5, GMC1TxD1, TBITxD5, RTBI1TxD1 EMCRxD0, ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name EOT0/TC0 EOT1/TC1 EOT2/TC2[GMCRxD2, GMC0RxD2, TBIRxD2, RTBI0RxD2] EOT3/TC3[GMCRxD3, GMC0RxD3, TBIRxD3, RTBI0RxD3] ExtAck[TrcTS2] ExtReq[TrcTS3] ExtReset [GMCCD, GMC1RxClk, RTBI1RxClk]TrcTS1[GPIO27] [GMCCrS, GMC1TxClk, RTBI1TxClk]TrcTS6 GMCRefClk [GMCRxD0, GMC0RxD0, TBIRxD0, RTBI0RxD0]DMAAck2 [GMCRxD1, GMC0RxD1, TBIRxD1, ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND 24 (Sheet 7 of 24) Ball Interface Group AA02 AA06 AA10 AA13 AA17 AA21 Power AC04 AC08 ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name [GPIO00]IRQ00 [GPIO01]IRQ01 [GPIO02]IRQ02 [GPIO03]IRQ03 [GPIO04]IRQ04 [GPIO05]IRQ05 [GPIO06]IRQ06 [GPIO07]IRQ07 [GPIO08]IRQ08 [GPIO09]IRQ09 [GPIO10]IRQ10 GPIO11[GMCTxClk, TBIRxClk1] [GPIO12]UART1_Rx [GPIO13]UART1_Tx [GPIO14]UART1_DSR/CTS [GPIO15]UART1_RTS/DTR [GPIO16]IIC1SClk [GPIO17]IIC1SDA [GPIO18]TrcBS0[IRQ13] [GPIO19]TrcBS1[IRQ14] [GPIO20]TrcBS2[IRQ15] [GPIO21]TrcES0[IRQ16] [GPIO22]TrcES1[IRQ17] [GPIO23]TrcES2 [GPIO24]TrcES3 [GPIO25]TrcES4 ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name Halt HoldAck[TrcTS4] HoldReq[TrcTS5] IIC0SClk IIC0SDA IIC1SClk[GPIO16] IIC1SDA[GPIO17] IRQ00[GPIO00] IRQ01[GPIO01] IRQ02[GPIO02] IRQ03[GPIO03] IRQ04[GPIO04] IRQ05[GPIO05] IRQ06[GPIO06] IRQ07[GPIO07] IRQ08[GPIO08] IRQ09[GPIO09] IRQ10[GPIO10] [IRQ11]PCIReq1 [IRQ12]PCIGnt1 [IRQ13][GPIO18]TrcBS0 [IRQ14][GPIO19]TrcBS1 [IRQ15][GPIO20]TrcBS2 [IRQ16][GPIO21]TrcES0 [IRQ17][GPIO22]TrcES1 26 (Sheet 9 ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 AMCC 440GX – Power PC 440GX Embedded Processor (Sheet 10 of 24) ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name PCIXAD00 PCIXAD01 PCIXAD02 PCIXAD03 PCIXAD04 PCIXAD05 PCIXAD06 PCIXAD07 PCIXAD08 PCIXAD09 PCIXAD10 PCIXAD11 PCIXAD12 PCIXAD13 PCIXAD14 PCIXAD15 PCIXAD16 PCIXAD17 PCIXAD18 PCIXAD19 PCIXAD20 PCIXAD21 PCIXAD22 PCIXAD23 PCIXAD24 PCIXAD25 PCIXAD26 PCIXAD27 ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name PCIXAD32 PCIXAD33 PCIXAD34 PCIXAD35 PCIXAD36 PCIXAD37 PCIXAD38 PCIXAD39 PCIXAD40 PCIXAD41 PCIXAD42 PCIXAD43 PCIXAD44 PCIXAD45 PCIXAD46 PCIXAD47 PCIXAD48 PCIXAD49 PCIXAD50 PCIXAD51 PCIXAD52 PCIXAD53 PCIXAD54 PCIXAD55 PCIXAD56 PCIXAD57 PCIXAD58 ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name PCIXC0[BE0] PCIXC1[BE1] PCIXC2[BE2] PCIXC3[BE3] PCIXC4[BE4] PCIXC5[BE5] PCIXC6[BE6] PCIXC7[BE7] PCIXCap PCIXClk PCIXDevSel PCIXFrame PCIXGnt0 PCIXGnt1[IRQ12] PCIXGnt2 PCIXGnt3 PCIXGnt4 PCIXGnt5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0 PCIXReq1[IRQ11] PCIXReq2 ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name PCIXStop PCIXTRDY PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name PerBLast PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4 PerCS5 PerCS6 PerCS7 36 (Sheet 19 of 24) Ball Interface Group C07 External Slave Peripheral U18 External Master Peripheral E17 L10 ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name PerPar0 PerPar1 PerPar2 PerPar3 PerReady[RcvrInh] PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PerWE RAS [RcvrInh]PerReady RefVEn ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name TrcBS0[GPIO18][IRQ13] TrcBS1[GPIO19][IRQ14] TrcBS2[GPIO20][IRQ15] TrcClk TrcES0[GPIO21][IRQ16] TrcES1[GPIO22][IRQ17] TrcES2[GPIO23] TrcES3[GPIO24] TrcES4[GPIO25] TrcTS0[GPIO26] TrcTS1[GPIO27][GMCCD, GMC1RxClk, RTBI1RxClk] [TrcTS1]BusReq TrcTS2[GPIO28][GMCRxD4, GMC1RxD0, TBIRxD4, RTBI1RxD0] [TrcTS2]ExtAck TrcTS3[GPIO29][GMCRxD5, GMC1RxD1, TBIRxD5, RTBI1RxD1] [TrcTS3]ExtReq TrcTS4[GPIO30][GMCRxD6, GMC1RxD2, TBIRxD6, ...
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Power PC 440GX Embedded Processor Signals Listed Alphabetically Signal Name UART0_Tx UART1_DSR/CTS[GPIO14] UART1_RTS/DTR[GPIO15] UART1_Rx[GPIO12] UART1_Tx[GPIO13] UARTSerClk ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name ...
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Power PC 440GX Embedded Processor In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed by Ball Assignment Ball Signal Name Ball E01 EMCRxD1 * F01 E02 PCIXAD40 F02 E03 PCIXClk F03 E04 PCIXAD49 F04 E05 UART1_RTS/DTR * F05 E06 PCIXAD56 F06 E07 PCIXAD60 F07 ...
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Power PC 440GX Embedded Processor Signals Listed by Ball Assignment Ball Signal Name Ball J01 APGND K01 J02 EMCRxClk * K02 J03 EMCTxD3 * K03 J04 EMCTxD2 * K04 J05 PCIXAD37 K05 J06 EMCTxClk * K06 J07 EMCCD ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed by Ball Assignment Ball Signal Name Ball N01 PerAddr08 P01 N02 GND P02 N03 PerAddr28 P03 V N04 P04 DD N05 DMAAck0 P05 N06 GND P06 N07 PerReady * P07 ...
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Power PC 440GX Embedded Processor Signals Listed by Ball Assignment Ball Signal Name Ball U01 TmrClk V01 U02 GND V02 U03 PerCS7 V03 OV U04 V04 DD U05 MemData63 V05 U06 GND V06 U07 MemData57 V07 V U08 ...
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Revision 1.19 – December 19, 2008 Data Sheet Signals Listed by Ball Assignment Ball Signal Name Ball AA01 MemData48 AB01 AA02 GND AB02 AA03 MemData49 AB03 V AA04 AB04 DD AA05 DQS8 AB05 AA06 GND AB06 AA07 DM5 AB07 SV ...
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... PPC440GX has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440GX. In this example, the pins are also bidirectional, serving both as inputs and outputs. ...
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Revision 1.19 – December 19, 2008 Data Sheet Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation ...
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Power PC 440GX Embedded Processor Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull ...
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Revision 1.19 – December 19, 2008 Data Sheet Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must ...
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Power PC 440GX Embedded Processor Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull ...
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... Used by slave peripherals to indicate they are prepared to transfer DMAReq0:3 data. EOT0:3/TC0:3 End Of Transfer/Terminal Count. Peripheral address bus used by PPC440GX when not in external master mode, otherwise used by external master. PerAddr00:31 Note: PerAddr00 is the most significant bit (msb) on this bus. PerWBE0:3 External peripheral data bus byte enables. ...
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... Note: PerData00 is the most significant bit (msb) on this bus. Used by either peripheral controller or DMA controller depending PerOE upon the type of transfer involved. When the PPC440GX is the bus master, it enables the selected device to drive the bus. PerPar0:3 External peripheral data bus byte parity. ...
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Revision 1.19 – December 19, 2008 Data Sheet Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must ...
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Power PC 440GX Embedded Processor Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull ...
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Revision 1.19 – December 19, 2008 Data Sheet Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must ...
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... Input Voltage (3.3V LVTTL receivers) Storage Temperature Range Case Temperature under bias Notes: 1. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GX. A separate filter, as shown below, is recommended for each voltage This value is not a specification of the operational temperature range ...
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Revision 1.19 – December 19, 2008 Data Sheet Package Thermal Specifications Thermal resistance values for the CBGA and PBGA packages in a convection environment are as follows: Parameter Junction-to-case thermal resistance Case-to-ambient thermal resistance (w/o heat sink) Junction-to-ball (typical) Notes: ...
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Power PC 440GX Embedded Processor Heat Sink Mounting Information (Ceramic Package Only) Proper thermal design is primarily dependent upon multiple system-level effects; that is, the effects of the heat sink, the air flow, and the thermal interface material. ...
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Revision 1.19 – December 19, 2008 Data Sheet Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Logic Supply Voltage (500MHz Rev A and 533MHz) ...
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... PCI-X drivers meet PCI-X specifications REF DD 3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GX. See “Absolute Maximum Ratings” on page 58. 4. There are the chip I/O pins before OV is applied to the chip ...
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... In general, the values are measured using a PPC440GX Evaluation Board set for Ethernet mode 4, PCI-X running at 100MHz with an Intel Pro 1000, an Agilent Test card, an EBMI test card, a UART wrap plug, and one 128MB Micron DIMM while running applications designed to maximize CPU power consumption ...
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Power PC 440GX Embedded Processor Clocking Specifications Symbol Parameter SysClk Input F Frequency C T Period C T Edge stability (cycle-to-cycle jitter High time CH T Low time CL Note: Input slew rate ≥ 1V/ns PLL ...
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Revision 1.19 – December 19, 2008 Data Sheet Timing Waveform T CH AMCC 440GX – Power PC 440GX Embedded Processor 2.0V 1.5V 0.8V 65 ...
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... Ethernet operation is unaffected. 3. IIC operation is unaffected. Important the system designer to ensure that any SSCG used with the PPC440GX meets the above requirements and does not adversely affect other aspects of the system. 66 Revision 1.19 – December 19, 2008 ...
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Revision 1.19 – December 19, 2008 Data Sheet Peripheral Interface Clock Timings Parameter PCIXClk input frequency (asynchronous mode) PCIXClk period (asynchronous mode) PCIXClk input high time PCIXClk input low time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk ...
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... OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of the OPB PLB clock. The maximum OPB clock frequency is 83.33 MHz. Refer to the Clocking chapter of the PPC440GX Embedded Processor User’s Manual for details. 2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz. ...
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Revision 1.19 – December 19, 2008 Data Sheet Input Setup and Hold Waveform Clock Inputs Output Delay and Float Timing Waveform Clock T max OV T min Outputs OH High (Drive) Float (High-Z) Low (Drive) AMCC 440GX – Power PC ...
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Power PC 440GX Embedded Processor Input Setup and Hold Waveform for RGMII Signals GMCnRxClk 1.25V Inputs RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnRxClk. RGMII 10/100Mb timing is with reference only to ...
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Revision 1.19 – December 19, 2008 Data Sheet I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is ...
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Power PC 440GX Embedded Processor I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns ...
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Revision 1.19 – December 19, 2008 Data Sheet I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is ...
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Power PC 440GX Embedded Processor I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns ...
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Revision 1.19 – December 19, 2008 Data Sheet I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is ...
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Power PC 440GX Embedded Processor I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns ...
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Revision 1.19 – December 19, 2008 Data Sheet I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is ...
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Power PC 440GX Embedded Processor I/O Specifications—500MHz–800MHz Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns. Input (ns) Setup Signal Time (T min) IS External Slave Peripheral ...
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... The signals are terminated as indicated in the figure below for the DDR timing data in the following sections. DDR SDRAM Simulation Signal Termination Model MemClkOut0 MemClkOut0 PPC440GX Addr/Ctrl/Data/DQS Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data not a recommended physical circuit design for this interface. An actual interface design will depend on many factors, including the type of memory used and the board layout ...
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Power PC 440GX Embedded Processor DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 RAS CAS WE BankSel0:3 ClkEn0:3 DQS0:8 80 Revision 1.19 – December ...
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Revision 1.19 – December 19, 2008 Data Sheet DDR SDRAM Write Operation The following diagram illustrates the relationship among the signals involved with a DDR write operation. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut0 MemClkOut0(90) Addr/Cmd DQS MemData T ...
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Power PC 440GX Embedded Processor I/O Timing—DDR SDRAM T Notes: 1. All of the DQS signals are referenced to MemClkOut0(0). 2. The T values in the table include 3 cycle at the indicated clock speed. DS ...
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Revision 1.19 – December 19, 2008 Data Sheet I/O Timing—DDR SDRAM T Notes referenced to MemClkOut0(0 obtain adjusted T values for lower clock frequencies, use 3/4 of the cycle time for the lower ...
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Power PC 440GX Embedded Processor I/O Timing—DDR SDRAM T Notes and T are measured under worst case conditions The time values in the table include 1 cycle at the indicated clock ...
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... In operation, following the receipt of an address and read command from the PPC440GX, the SDRAM generates data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GX using a DQS signal that is delayed 1 cycle. In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency ...
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Power PC 440GX Embedded Processor I/O Timing—DDR SDRAM T Notes Delay from DQS at package pin Stage 1 FF. SIN Delay from data at package pin ...
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... Except for small, low frequency memory systems with the memory located physically close to the PPC440GX unlikely that Stage 1 data can be sampled. When the data comes later necessary to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing ...
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Power PC 440GX Embedded Processor Example 2: In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC is enabled, Stage 3 data must be sampled (see ...
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Revision 1.19 – December 19, 2008 Data Sheet Example 3: In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system will still work, but there will be more ...
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... Power PC 440GX Embedded Processor Initialization The PPC440GX provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered by strapping on external pins (see “Strapping” below). ...
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Revision 1.19 – December 19, 2008 Data Sheet Revision Log Date 08/07/2002 Add revision log. Change EMC0:1TxD0:1 and EMC0:1TxEn T 08/30/2002 09/25/2002 Update for L2 cache 10/22/2002 Add heat sink mounting information . 11/20/2002 Update I/O timing data. Update PCI-X ...
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... Remove power supply power-up sequence requirements. 07/16/2008 Change package type to ceramic for PPC440GX-3RF400C (Doc Issue 549). Doc Issue 408. Rename AGND pins according to the analog voltage with which they are associated. 09/16/2008 Doc Issue 483. Add two RGMII I/O timing waveforms. ...
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Revision 1.19 – December 19, 2008 Data Sheet Printed in the United States of America, Thursday, January 08, 2009 The following are trademarks of AMCC in the United States, or other countries, or both: AMCC Other company, product, and service ...
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... AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2008 Applied Micro Circuits Corporation. 94 Applied Micro Circuits Corporation 215 Moffett Park Drive, Sunnyvale, CA 94089 http://www.amcc.com Revision 1.19 – ...