PPC440GX-3RF667C Applied Micro Circuits Corporation, PPC440GX-3RF667C Datasheet - Page 72

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PPC440GX-3RF667C

Manufacturer Part Number
PPC440GX-3RF667C
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of PPC440GX-3RF667C

Family Name
440GX
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
667MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.55/2.5V
Operating Supply Voltage (max)
1.6/2.7V
Operating Supply Voltage (min)
1.5/2.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
552
Package Type
CBGA
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PPC440GX-3RF667C
Manufacturer:
BROADCOM
Quantity:
1 001
Part Number:
PPC440GX-3RF667C
Manufacturer:
AMCC
Quantity:
1 045
I/O Specifications—All Speeds
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
440GX – Power PC 440GX Embedded Processor
72
Ethernet SMII Interface
EMC0:1RxD
EMC2:3RxD
EMC0:1TxD
EMC2:3TxD
EMCRefClk
Ethernet GMII Interface
GMCRxClk
GMCRxD0:7
GMCRxEr
GMCRxDV
GMCCrS
GMCol
GMCGTxClk
GMCTxD0:7
GMCTxEr
GMCTxEn
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
Signal
Setup Time
(T
IS
0.8
0.8
na
na
na
na
na
na
na
na
2
2
2
min)
Input (ns)
Hold Time
(T
IH
0.8
0.8
na
na
na
na
na
na
na
na
0
0
0
min)
(Sheet 3 of 7)
Valid Delay
(T
OV
3.5
3.5
5.5
5.5
5.5
na
na
na
na
na
na
na
na
na
na
max)
Output (ns)
Hold Time
(T
OH
0.5
0.5
0.5
na
na
na
na
na
na
na
na
na
na
2
2
min)
(minimum)
Output Current (mA)
I/O H
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
na
na
na
(minimum)
Revision 1.20 – June 9, 2009
I/O L
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
na
na
na
GMCGTxClk
GMCGTxClk
GMCGTxClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
GMCRxClk
GMCRxClk
GMCRxClk
Data Sheet
Clock
Notes
async
async
async
async
async
AMCC
4,
1,
1,
1,
1,

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