PPC440GX-3RF667C Applied Micro Circuits Corporation, PPC440GX-3RF667C Datasheet - Page 71

• Manufacturer Part Number: PPC440GX-3RF667C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3RF667C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.55/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.5/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: CBGA
• Lead Free Status / RoHS Status: Compliant

I/O Specifications—All Speeds
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Revision 1.20 – June 9, 2009
AMCC
Ethernet MII Interface
EMCRxD0:3
EMCRxDV
EMCRxClk
EMCRxErr
EMCTxD0:3
EMCTxEn
EMCTxClk
EMCTxErr
EMCCrS
EMCCD
EMCMDIO
EMCMDClk
Ethernet RMII Interface
EMC0RxD0:1
EMC0RxErr
EMC0CrSDV
EMC0TxD0:1
EMC0:1TxEn
EMC1RxD0:1
EMC1RxErr
EMC1CrSDV
EMC1TxD0:1
EMCRefClk
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
Data Sheet
Signal
Setup Time
(T
IS
na
na
na
na
na
na
na
na
na
na
4
4
4
2
2
min)
Input (ns)
Hold Time
(T
IH
na
na
na
na
na
na
na
na
na
na
1
1
1
1
1
min)
(Sheet 2 of 7)
Valid Delay
(T
OV
na
na
na
na
15
15
na
15
na
na
na
na
na
na
11
11
na
na
na
11
na
max)
Output (ns)
440GX – Power PC 440GX Embedded Processor
Hold Time
(T
OH
na
na
na
na
na
na
na
na
na
na
na
na
na
na
na
2
2
2
2
2
2
min)
(minimum)
Output Current (mA)
I/O H
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
na
na
(minimum)
I/O L
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
6.8
na
na
EMCMDClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRefClk
EMCRxClk
EMCRxClk
EMCRxClk
EMCTxClk
EMCTxClk
EMCTxClk
Clock
Notes
async
async
async
async
async
async
1,
1,
1,
1,
1,
3,
1
1
1
1
1
1
1
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