PPC440EP-3JC533C Applied Micro Circuits Corporation, PPC440EP-3JC533C Datasheet - Page 78

• Manufacturer Part Number: PPC440EP-3JC533C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EP-3JC533C

• Family Name: 440EP
• Device Core: PowerPC
• Device Core Size: 16b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Lead Free Status / RoHS Status: Compliant

Note: The timing data in the following tables is based on simulation runs using Einstimer.
Table 22. I/O Timing—DDR SDRAM T
Notes:
1. All of the DQS signals are referenced to MemClkOut0(0).
2. Clock speed is 133MHz.
3. The T
4. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle
Table 23. I/O Timing—DDR SDRAM T
Notes:
1. Clock speed is 133MHz. T
2. To obtain adjusted T
3. To obtain adjusted T
Table 24. I/O Timing—DDR SDRAM T
Notes:
1. T
2. Clock speed for the values in the table is 133MHz.
3. The time values in the table include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
4. To obtain adjusted T
78
DQS0
DQS1
DQS2
DQS3
DQS8
MemAddr00:12
BA0:1
BankSel0:3
ClkEn0:3
CAS
RAS
WE
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
ECC0:7, DM8
Revision 1.29 – May 07, 2008
T
T
1/4 of the cycle time for the lower clock frequency (e.g., T
time for the lower clock frequency (T
SD
SK
SK
maximum (0.75T
minimum (0.25T
and T
DS
Signal Names
Data Sheet
values in the table include 3/4 of a cycle at 133MHz (7.5ns x 0.75 = 5.625 ns).
HD
Signal Name
Signal Name
are measured under worst case conditions.
SA
HA
SD
CYC
CYC
values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and subtract
values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add
and T
+ T
- T
SK
SK
SK
HD
is referenced to MemClkOut0(0). T
max).
min).
values for lower clock frequencies, subtract 1.875 ns from the values in the table and add
DS
Reference Signal
- 5.625 + 0.75T
DS
SK
SD
DQS0
DQS1
DQS2
DQS3
DQS8
, T
and T
SA
Minimum
, and T
0.11
0.07
0.05
0.07
0.05
0.05
0.08
HD
CYC
Minimum
HA
T
SD
SK
5.76
5.78
5.82
5.79
5.75
).
- 1.875 + 0.25T
(ns)
SA
440EP – PPC440EP Embedded Processor
Maximum
and T
0.32
0.31
0.25
0.28
0.31
0.28
0.22
T
HA
SD
1.795
1.775
1.745
1.765
1.685
CYC
are referenced to MemClkOut0(90).
(ns)
T
DS
).
(ns)
Minimum
T
SA
5.31
5.32
5.38
5.35
5.32
5.35
5.41
(ns)
Maximum
5.86
5.91
5.90
5.89
5.88
T
HD
1.866
1.865
1.862
1.864
1.857
AMCC Proprietary
(ns)
Minimum
T
HA
1.99
1.95
1.93
1.95
1.93
1.93
1.96
(ns)